Rev X.00

Page 1 of 8

Jan 13, 2017

Rev X.00

Jan 13, 2017

CD40174BMS

CMOS Hex ‘D’-Type Flip-Flop

DATASHEET

Pinout

CD40174BMS

TOP VIEW

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

CLEAR

Q1

D1

D2

Q2

D3

VSS

Q3

VDD

D6

D5

Q5

D4

Q4

CLOCK

Q6

F/F1

F/F2

D1

3

D2

4

Q2

5

Q1

2

F/F3

D3

6

Q3

7

F/F4

D4

11

Q4

10

F/F5

D5

13

Q5

12

F/F6

D5

14

Q6

15

CLOCK

9

CLEAR

1

VSS = 8

VDD = 16

Features

• High Voltage Type (20V Rating)

• 5V, 10V and 15V Parametric Ratings

• Standardized, Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1

A at 18V Over Full Pack-

age Temperature Range, 100nA at 18V and +25oC

• Noise Margin (Over full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13A, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• Shift Registers

• Buffer/Storage Registers

• Pattern Generators

Description

CD40174BMS consists of six identical ‘D’-Type flip-flops

having independent DATA inputs. The CLOCK and CLEAR

inputs are common to all six units. Data is transferred to the

Q outputs on the positive going transition of the clock pulse.

All six flip-flops are simultaneously reset by a low level on

the CLEAR input.

The CD40174BMS is supplied in these 16 lead outline pack-

ages:

Braze Seal DIP

H4T

Frit Seal DIP

H1E

Ceramic Flatpack

H6W