FN3317 Rev 0.00

Page 1 of 9

December 1992

FN3317

Rev 0.00

December 1992

CD4060BMS

CMOS 14 Stage Ripple-Carry Binary Counter/Divider and Oscillator

DATASHEET

Pinout

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

Q12

Q13

Q14

Q6

Q5

Q7

VSS

Q4

VDD

Q8

Q9

RESET

øI

ø0

ø0

Q10

7

14 STAGE

RIPPLE

COUNTER

AND

OSCILLATOR

5

4

6

14

13

15

1

2

3

9

10

11

12

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q12

Q13

Q14

R

øI

ø0

ø0

VSS = 8

VDD = 16

Features

• High Voltage Type (20V Rating)

• Common Reset

• 12MHz Clock Rate at 15V

• Fully Static Operation

• Buffered Inputs and Outputs

• Schmitt Trigger Input Pulse Line

• Standardized, Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Oscillator Features

• All Active Components on Chip

• RC or Crystal Oscillator Configuration

• RC Oscillator Frequency of 690kHz Min. at 15V

Applications

• Control counters

•Timers

• Frequency Dividers

• Time Delay Circuits

Description

CD4060BMS consists of an oscillator section and 14 ripple

carry binary counter stages. The oscillator configuration allows

design of either RC or crystal oscillator circuits. A RESET input

is provided which resets the counter to the all O’s state and dis-

ables the oscillator. A high level on the RESET line accom-

plishes the reset function. All counter stages are master slave

flip-flops. The state of the counter is advanced one step in

binary order on the negative transition of øI (and ø0). All inputs

and outputs are fully buffered. Schmitt trigger action on the

input pulse line permits unlimited input pulse rise and fall times.

The CD4060BMS is supplied in these 16 lead outline pack-

ages:

Braze Seal DIP

H4W

Frit Seal DIP

H1F

Ceramic Flatpack

H6W