83C554 datasheet(9/76 Pages) PHILIPS

9 / 76 page

Philips Semiconductors

Preliminary specification

80C554/83C554/87C554

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,

capture/compare, high I/O, 64L LQFP

2000 Nov 10

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an on-chip

oscillator, as shown in the logic symbol.

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. The minimum and maximum

high and low times specified in the data sheet must be observed.

RESET

A reset is accomplished by either (1) externally holding the RST pin

high for at least two machine cycles (12 oscillator periods) or (2)

internally by an on-chip power-on detect (POD) circuit which detects

VCC ramping up from 0 V.

To insure a good external power-on reset, the RST pin must be high

long enough for the oscillator to start up (normally a few

milliseconds) plus two machine cycles. The voltage on VDD and the

RST pin must come up at the same time for a proper startup.

For a successful internal power-on reset, the VCC voltage must

ramp up from 0 V smoothly at a ramp rate greater than 5 V/100 ms.

The RST line can also be pulled HIGH internally by a pull-up

transistor activated by the watchdog timer T3. The length of the

output pulse from T3 is 3 machine cycles. A pulse of such short

duration is necessary in order to recover from a processor or system

fault as fast as possible.

Note that the short reset pulse from Timer T3 cannot discharge the

power-on reset capacitor (see Figure 2). Consequently, when the

watchdog timer is also used to set external devices, this capacitor

arrangement should not be connected to the RST pin, and a

different circuit should be used to perform the power-on reset

operation. A timer T3 overflow, if enabled, will force a reset condition

to the 8xC554 by an internal connection, independent of the level of

the RST pin.

A reset may be performed in software by setting the software reset

bit, SRST (AUXR1.5).

VDD

RRST

RST

SCHMITT

TRIGGER

RESET

CIRCUITRY

ON-CHIP

RESISTOR

OVERFLOW

TIMER T3

SU00952

Figure 1. On-Chip Reset Configuration

RRST

VDD

2.2

µF

8XC554

RST

SU00953

Figure 2. Power-On Reset

LOW POWER MODES

Stop Clock Mode

The static design enables the clock speed to be reduced down to

0 MHz (stopped). When the oscillator is stopped, the RAM and

Special Function Registers retain their values. This mode allows

step-by-step utilization and permits reduced system power

consumption by lowering the clock frequency down to any value. For

lowest power consumption the Power Down mode is suggested.

Idle Mode

In the idle mode (see Table 2), the CPU puts itself to sleep while

some of the on-chip peripherals stay active. The instruction to

invoke the idle mode is the last instruction executed in the normal

operating mode before the idle mode is activated. The CPU

contents, the on-chip RAM, and all of the special function registers

remain intact during this mode. The idle mode can be terminated

either by any enabled interrupt (at which time the process is picked

up at the interrupt service routine and continued), or by a hardware

reset which starts the processor in the same manner as a power-on

reset.

Power-Down Mode

To save even more power, a Power Down mode (see Table 2) can

be invoked by software. In this mode, the oscillator is stopped and

the instruction that invoked Power Down is the last instruction

executed. The on-chip RAM and Special Function Registers retain

their values down to 2.0 V and care must be taken to return VCC to

the minimum specified operating voltages before the Power Down

Mode is terminated.

Either a hardware reset or external interrupt can be used to exit from

Power Down. The Wake-up from Power-down bit, WUPD (AUXR1.3)

must be set in order for an external interrupt to cause a wake-up

from power-down. Reset redefines all the SFRs but does not

change the on-chip RAM. An external interrupt allows both the SFRs

and the on-chip RAM to retain their values.

To properly terminate Power Down the reset or external interrupt

should not be executed before VCC is restored to its normal

operating level and must be held active long enough for the

oscillator to restart and stabilize (normally less than 10 ms).

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