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P80C851FBA Datasheet(PDF) 13 Page - NXP Semiconductors |
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P80C851FBA Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 22 page ![]() Philips Semiconductors Product specification 80C851/83C851 CMOS single-chip 8-bit microcontroller with on-chip EEPROM 1998 Jul 03 13 AC ELECTRICAL CHARACTERISTICS1, 2 24 MHz Version 24MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 4 Oscillator frequency 3.5 24 MHz tLHLL 4 ALE pulse width 43 2tCLCL–40 ns tAVLL 4 Address valid to ALE low 17 tCLCL–25 ns tLLAX 4 Address hold after ALE low 17 tCLCL–25 ns tLLIV 4 ALE low to valid instruction in 102 4tCLCL–65 ns tLLPL 4 ALE low to PSEN low 17 tCLCL–25 ns tPLPH 4 PSEN pulse width 80 3tCLCL–45 ns tPLIV 4 PSEN low to valid instruction in 65 3tCLCL–60 ns tPXIX 4 Input instruction hold after PSEN 0 0 ns tPXIZ 4 Input instruction float after PSEN 17 tCLCL–25 ns tAVIV 4 Address to valid instruction in 128 5tCLCL–80 ns tPLAZ 4 PSEN low to address float 10 10 ns Data Memory tRLRH 5 RD pulse width 150 6tCLCL–100 ns tWLWH 5 WR pulse width 150 6tCLCL–100 ns tRLDV 5 RD low to valid data in 118 5tCLCL–90 ns tRHDX 5 Data hold after RD 0 0 ns tRHDZ 5 Data float after RD 55 2tCLCL–28 ns tLLDV 5 ALE low to valid data in 183 8tCLCL–150 ns tAVDV 5 Address to valid data in 210 9tCLCL–165 ns tLLWL 5, 6 ALE low to RD or WR low 75 175 3tCLCL–50 3tCLCL+50 ns tAVWL 5, 6 Address valid to RD or WR low 92 4tCLCL–75 ns tQVWH 6 Data setup time before WR 162 7tCLCL–130 ns tQVWX 6 Data valid to WR transition 12 tCLCL–30 ns tWHQX 6 Data hold after WR 17 tCLCL–25 ns tRLAZ 5 RD low to address float 0 0 ns tWHLH 5, 6 RD or WR high to ALE high 17 67 tCLCL–25 tCLCL+25 ns External Clock tCHCX 8 High time 17 17 ns tCLCX 8 Low time 17 17 ns tCLCH 8 Rise time 5 20 ns tCHCL 8 Fall time 5 20 ns Erase/write timer constant3 tE/W Erase/write cycle time 4 20 4 20 ms tE Erase time 2 10 2 10 ms tW Write time 2 10 2 10 ms tS Data retention time4 10 10 years NE/W Erase/write cycles5 10,000 10,000 cycles NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. The power-off fall-time of VDD must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause spurious parasitic writing to EEPROM cells. If the VDD power-off full-time is greater than 1ms, a power-off reset signal should be generated to prevent this condition from occurring. 4. Test condition: Tamb = +55°C. 5. Number of erase/write cycles for each EEPROM byte. |
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