DA16200 datasheet(59/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

59 of 153

Parameter

Symbol

Fast Mode

High Speed Mode

Unit

Min

Max

Min

Max

High period of the SCL clock

THIGH

1.23

0.45

μs

Setup time for START condition

TSU;STA

1.1

0.37

μs

Data hold time

THD;DAT

3x Top_clk

(Note 3)

3x Top_clk

(Note 3)

μs

Data setup time

TSU;DAT

TLOW

- THD;DAT

TLOW

- THD;DAT

μs

Rise time of both SDA and SCL

(Note 4)

0.02

0.3

0.05

μs

Setup time for STOP condition

TSU;STO

0.36

0.45

μs

Data valid acknowledge time

TVD;ACK

3x Top_clk

(Note 3)

3x Top_clk

(Note 3)

μs

Buffer free time between

START and STOP condition

TBUF

0.5

μs

Note 1

Clock duty ratio = (THIGH /TSCLK) × 100[%], TSCLK = 1/FSCLK.

Note 2

Max. clock = 3.4 MHz (TSCLK = 294 ns) over 40 MHz of the Fop_clk.

Max. clock = 1.0 MHz (TSCLK = 1000 ns) under 40 MHz of the Fop_clk.

Note 3

Top_clk = (1 / Fop_clk ) x 106

μsec.

Note 4

TR depends on a pull-up resistor value.

9.5.2

I2C Slave

The I2C slave interface provides support for an external host to control the DA16200. The pin mux

configuration is defined in Table 44.

Four ranges of clock speed are supported: standard (100 kHz), fast (400 kHz), fast plus (1.0 MHz)

and High Speed (3.4 MHz).

Table 44: I2C Slave Pin Configuration

Pin Name

Pin Number

I/O

Function Name

QFN

fcCSP

GPIOA1

I2C_CLK

GPIOA3

GPIOA5

GPIOA7

GPIOA0

I/O

I2C_SDA

GPIOA2

I/O

GPIOA4

I/O

GPIOA6

I/O

Figure 34 shows the I2C slave timing diagram.

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