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DA16200 Datasheet(PDF) 149 Page - Renesas Technology Corp |
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DA16200 Datasheet(HTML) 149 Page - Renesas Technology Corp |
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149 / 154 page ![]() DA16200 Ultra Low Power Wi-Fi SoC Datasheet Revision 3.6 04-Jan-2023 CFR0011-120-00 149 of 153 © 2023 Renesas Electronics Revision History Revision Date Description 3.6 04-Jan-2023 ● Section 7.5.1, 9.8.4, Table 28 added details for sleep modes ● Updated operating temperature in Key Features list ● Updated Table 4 to add storage temperature range and adjusted min/max voltages 3.5 13-Jun-2022 ● Section 7.3.1.2 Corrected the internal SRAM address range ● Section 7.4.2 Added note about Sleep mode 2 &3 for retention I/O ● Section 9.3 and Section 10.5 Added note about SPI slave half- duplex and clock speed calculation ● Table 32 Changed to Chacha20 and Poly1305 ● Table 52 Removed Input Tolerance 3.4 17-Jan-2022 ● Section 4.3 Updated Pinout Multiplexing ● Section 5.8 Updated Clock Electrical Characteristics ● Section 9.3 fixed typo ● Section 9.4 Added SDIO interface needs pull-up resistors description and Figure 32 ● Section 9.5.3 Added I2C Interface Pull-up ● Section 9.12 Updated SWD part Table 60 ● Section 11.3 and 11.4 Updated Description ● Update to the operating temperature range ● Updates to for variant 001. (OTP Size, BT Coex, BOR registers) ● Table 8 Updated the Guaranteed logic High level VIH to 2,3V 3.3 03-Fab-2021 ● Table 1 Updated Pinout Description ● Section 6.1 Added Note for Power on Sequence and Updated Table 26 and Figure 11 ● Section 9.7.3 Fixed typo ● Section 10 Updated RC Delay Description (Table 61, Table 63, Table 65, Table 67 and Figure 56, Figure 57, Figure 58, Figure 59) 3.2 28-Sep-2020 ● Section 6.3 Updated Sleep mode Description ● Removed F_xx pins in Interface Parts. ● Section 4.3 (Table 3) Updated Pin Multiplexing ● Section 9.8 (Table 52) Updated ADC Reference Voltage ● Section 9.5.1 and 9.5.2 Updated I2C Speed Description ● Section 9.5 Updated I2C interface (Table 43) and (Table 45) ● Section 9.7.1 and 9.7.2 Added, I2S Description, Block Diagram, and Clock Scheme ● Section 9.8.2 Table 52 Swapped SNDR, SNR value |
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