P80C552IFA datasheet(20/23 Pages) PHILIPS

20 / 23 page

Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

2002 Sep 03

SU01704

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

VDD

P1.6

P1.7

STADC

AVSS

AVref–

Figure 12. IDD Test Condition, Active Mode

All other pins are disconnected1

SU01705

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

VDD

P1.6

P1.7

STADC

AVSS

AVref–

Figure 13. IDD Test Condition, Idle Mode

All other pins are disconnected2

SU01706

VDD–0.5

0.5 V

0.7VDD

0.2VDD–0.1

tCHCL

tCLCL

tCLCH

tCLCX

tCHCX

Figure 14. Clock Signal Waveform for IDD Tests in Active and

Idle Modes tCLCH = tCHCL = 5ns

SU01707

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

VDD

P1.6

P1.7

STADC

AVSS

AVref–

Figure 15. IDD Test Condition, Power Down Mode

All other pins are disconnected. VDD = 2 V to 5.5 V3

NOTES:

1. Active Mode:

a. The following pins must be forced to VDD: EA, RST, Port 0, and EW.

b. The following pins must be forced to VSS: STADC, AVss, and AVref–.

c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the IOL1 spec of these pins.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

2. Idle Mode:

a. The following pins must be forced to VDD: Port 0 and EW.

b. The following pins must be forced to VSS: RST, STADC, AVss,, AVref–, and EA.

c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

3. Power Down Mode:

a. The following pins must be forced to VDD: Port 0 and EW.

b. The following pins must be forced to VSS: RST, STADC, XTAL1, AVss,, AVref–, and EA.

c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

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