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P80C552IFA Datasheet(PDF) 14 Page - NXP Semiconductors |
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P80C552IFA Datasheet(HTML) 14 Page - NXP Semiconductors |
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14 / 24 page  Philips Semiconductors Product specification 80C552/83C552 Single-chip 8-bit microcontroller 1998 Aug 13 14 AC ELECTRICAL CHARACTERISTICS (Continued)1, 2 24/30 MHz version 24MHz CLOCK 30MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT 1/tCLCL 2 Oscillator frequency 3.5 24 MHz tLHLL 2 ALE pulse width 43 27 2tCLCL–40 ns tAVLL 2 Address valid to ALE low 17 8 tCLCL–25 ns tLLAX 2 Address hold after ALE low 17 8 tCLCL–25 ns tLLIV 2 ALE low to valid instruction in 102 68 4tCLCL–65 ns tLLPL 2 ALE low to PSEN low 17 8 tCLCL–25 ns tPLPH 2 PSEN pulse width 80 55 3tCLCL–45 ns tPLIV 2 PSEN low to valid instruction in 65 40 3tCLCL–60 ns tPXIX 2 Input instruction hold after PSEN 0 0 0 ns tPXIZ 2 Input instruction float after PSEN 17 8 tCLCL–25 ns tAVIV 2 Address to valid instruction in 128 87 5tCLCL–80 ns tPLAZ 2 PSEN low to address float 10 10 10 ns Data Memory tRLRH 3 RD pulse width 150 100 6tCLCL–100 ns tWLWH 4 WR pulse width 150 100 6tCLCL–100 ns tRLDV 3 RD low to valid data in 118 77 5tCLCL–90 ns tRHDX 3 Data hold after RD 0 0 0 ns tRHDZ 3 Data float after RD 55 39 2tCLCL–28 ns tLLDV 3 ALE low to valid data in 183 117 8tCLCL–150 ns tAVDV 3 Address to valid data in 210 135 9tCLCL–165 ns tLLWL 3, 4 ALE low to RD or WR low 75 175 50 150 3tCLCL–50 3tCLCL+50 ns tAVWL 3, 4 Address valid to WR low or RD low 92 58 4tCLCL–75 ns tQVWX 4 Data valid to WR transition 12 3 tCLCL–30 ns tDW 4 Data before WR 162 103 7tCLCL–130 ns tWHQX 4 Data hold after WR 17 8 tCLCL–25 ns tRLAZ 3 RD low to address float 0 0 0 ns tWHLH 3, 4 RD or WR high to ALE high 17 67 8 58 tCLCL–25 tCLCL+25 ns External Clock tCHCX 5 High time3 17 15 17 ns tCLCX 5 Low time3 17 15 17 ns tCLCH 5 Rise time3 5 3 20 ns tCHCL 5 Fall time3 5 3 20 ns Serial Timing – Shift Register Mode3 (Test Conditions: Tamb = 0°C to +70°C; VSS = 0V; Load Capacitance = 80pF) tXLXL 6 Serial port clock cycle time 0.5 0.4 12tCLCL µs tQVXH 6 Output data setup to clock rising edge 283 200 10tCLCL–133 ns tXHQX 6 Output data hold after clock rising edge 23 6.6 2tCLCL–60 ns tXHDX 6 Input data hold after clock rising edge 0 0 0 ns tXHDV 6 Clock rising edge to input data valid 283 200 10tCLCL–133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. These values are characterized but not 100% production tested. 4. tCLCL = 1/fOSC = one oscillator clock period. tCLCL = 41.7ns at fOSC = 24MHz. |
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