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85352AYILF Datasheet(PDF) 4 Page - Renesas Technology Corp

Part # 85352AYILF
Description  12 Bit, 2-to-1, 3.3V, 2.5V LVPECL Clock Buffer
PDF  21 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

85352AYILF Datasheet(HTML) 4 Page - Renesas Technology Corp

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©2015 Integrated Device Technology, Inc.
Revision C, December 1, 2015
85352 Datasheet
Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VCCO = 2.5V to 3.3V ±5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: Outputs terminated with 50
 to V
CCO – 2V.
AC Electrical Characteristics
Table 5A. AC Electrical Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Table 5B. AC Electrical Characteristics, VCC = 3.3V ± 5%, VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCCO – 1.4
VCCO – 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO – 2.0
VCCO – 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
700
MHz
tPD
Propagation Delay; NOTE 1
1.0
1.5
2.0
ns
tjit
Buffer Additive Phase Jitter, RMS:
refer to additive Phase Jitter Section
156.25MHz
Integration Range: (12kHz – 20MHz)
0.21
ps
tsk(o)
Output Skew; NOTE 2, 3
180
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 4
750
ps
tR / tF
Output Rise/ Fall Time
20% to 80%
150
700
ps
odc
Output Duty Cycle
ƒ
 622MHz
45
55
%
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
700
MHz
tPD
Propagation Delay; NOTE 1
1.0
1.5
2.0
ns
tjit
Buffer Additive Phase Jitter, RMS
156.25MHz
Integration Range: (12kHz – 20MHz)
0.23
ps
tsk(o)
Output Skew; NOTE 2, 3
180
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 4
750
ps
tR / tF
Output Rise/ Fall Time
20% to 80%
150
700
ps
odc
Output Duty Cycle
ƒ
 622MHz
45
55
%



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