DA9313 datasheet(49/58 Pages) RENESAS

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DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.5

23-Feb-2022

CFR0011-120-00

49 of 57

Table 31: CONFIG_A 0x11

Bit

Mode

Symbol

Description

Reset

7:5

R/W

VBAT_UV_HYS

Programmable hysteresis for the critical

undervoltage threshold:

000: 50 mV

001: 100 mV

010: 150 mV

011: 200 mV

100: 250 mV

101: 300 mV

110: 350 mV

111: 400 mV

0x3

4:0

R/W

VBAT_UV_CRIT_TH

RSH

Note: PVC design requires 5.0 V minimum setting

for correct operation:

00000: 4.60 V

00001: 4.65 V

00010: 4.70 V

00011: 4.75 V

01000: 5.00 V

11100: 6.00 V

11101: 6.05 V

11110: 6.10 V

11111: 6.15 V

0x0

Table 32: CONFIG_C 0x13

Bit

Mode

Symbol

Description

Reset

R/W

VDDIO_EN

0: VDDIO LDO disabled, pads supplied from

VCORE

1: VDDIO LDO enabled, pads supplied at level set

via VDDIO_CONF

Note: When VDDIO_EN == 0, open drain GPO

configurations via GPIO_1_PIN or GPIO_0_PIN

valid only

0x1

6:5

R/W

FAULT_TIME

System controller configurable, pause when power

cycling to ensure discharge of all critical nodes in

the application before any attempt to reboot.

00: 0 ms (wait disable)

01: 10 ms

10: 100 ms

11: 500 ms

0x2

4:3

R/W

VDDIO_CONF

Selects the internal generated VDDIO voltage:

00: 1.5 V

01: 1.8 V

10: 2.8 V

11: 3.3 V

0x3

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