DSPIC30F datasheet(49/248 Pages) MICROCHIP

49 / 248 page

 2004 Microchip Technology Inc.

Preliminary

DS70083G-page 47

dsPIC30F

4.0

ADDRESS GENERATOR UNITS

The dsPIC core contains two independent address

generator units: the X AGU and Y AGU. Further, the X

AGU has two parts: X RAGU (Read AGU) and X

WAGU (Write AGU). The X RAGU and X WAGU sup-

port byte and word sized data space reads and writes

for both MCU and DSP instructions. The Y AGU sup-

ports word sized data reads for the DSP MAC class of

instructions only. They are each capable of supporting

two types of data addressing:

• Linear Addressing

• Modulo (Circular) Addressing

In addition, the X WAGU can support:

• Bit-Reversed Addressing

Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-reversed

addressing is only applicable to data space addresses.

4.1

Data Space Organization

Although the data space memory is organized as 16-bit

words,

all

effective

addresses

(EAs)

are

byte

addresses. Instructions can thus access individual

bytes as well as properly aligned words. Word

addresses must be aligned at even boundaries. Mis-

aligned word accesses are not supported, and if

attempted, will initiate an address error trap.

When executing instructions which require just one

source operand to be fetched from data space, the X

RAGU and X WAGU are used to calculate the effective

address. The X RAGU and X WAGU can generate any

address in the 64-Kbyte data space. They support all

MCU Addressing modes and modulo addressing for

low overhead circular buffers. The X WAGU also sup-

ports bit-reversed addressing to facilitate FFT data

reorganization.

When executing instructions which require two source

operands to be concurrently fetched (i.e., the MAC class

of DSP instructions), both the X RAGU and Y AGU are

used simultaneously and the data space is split into two

independent address spaces, X and Y. The Y AGU sup-

ports register indirect post-modified and modulo

addressing only.

In the Split Data Space mode, some W register address

pointers are dedicated to X RAGU, and others to Y

AGU. The EAs of each operand must, therefore, be

restricted within different address spaces. If they are

not, one of the EAs will be outside the address space

of the corresponding data space (and will fetch the bus

default value, 0x0000).

4.2

Instruction Addressing Modes

The Addressing modes in Table 4-1 form the basis of

the Addressing modes optimized to support the specific

features of individual instructions. The Addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

Some Addressing mode combinations may lead to a

one-cycle stall during instruction execution, or are not

allowed, as discussed in Section 4.3.

TABLE 4-1:

FUNDAMENTAL ADDRESSING MODES SUPPORTED

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the dsPIC30F Family Reference

Manual (DS70046). For more information on the device

instruction set and programming, refer to the dsPIC30F

Programmer’s Reference Manual (DS70030).

Note:

The data write phase of the MAC class of

instructions does not split X and Y address

space. The write EA is calculated using

the X WAGU and the data space is

configured for full 64-Kbyte access.

Addressing Mode

Description

File Register Direct

The address of the File register is specified explicitly.

The contents of a register are accessed directly.

The contents of Wn forms the EA.

The contents of Wn forms the EA. Wn is post-modified (incremented or

decremented) by a constant value.

Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.

The sum of Wn and a literal forms the EA.

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