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MPC9608 Datasheet(PDF) 2 Page - Renesas Technology Corp |
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MPC9608 Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 14 page ![]() MPC9608 REVISION 4 MARCH 15, 2016 2 ©2016 Integrated Device Technology, Inc. MPC9608 Data Sheet 1:10 LVCMOS ZERO DELAY CLOCK BUFFER Figure 1. MPC9608 Logic Diagram PLL FB_IN QA0 QA1 QA2 QA3 QA4 Ref FB CCLK QFB 2 2 QB0 QB1 QB2 QB3 QB4 Bank A Bank B PLL feedback BSEL CLK_STOP VCO CCLK STOP F_RANGE[0:1] 00: 100-200 MHz 01: 50-100 MHz 10: 25- 50 MHz 11:12.5- 25 MHz 25k 25k 25k 25k 25k 25k 25k OE PLL_EN VCC QA4 QA3 QA2 GND QA1 QA0 VCC QB4 QB3 QB2 GND QB1 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 123 4567 8 24 23 22 21 20 19 18 17 16 MPC9608 VCC QB0 VCC Figure 2. MPC9608 32-Lead Package Pinout (Top View) |
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