REVISION 8 3/16/16

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©2016 INTEGRATED DEVICE TECHNOLOGY, INC.

MPC9772 DATA SHEET

Table 1. Pin Configuration

Pin

I/O

Type

Function

CCLK0

Input

LVCMOS

PLL reference clock

CCLK1

Input

LVCMOS

Alternative PLL reference clock

XTAL_IN, XTAL_OUT

Analog

Crystal oscillator interface

FB_IN

Input

LVCMOS

PLL feedback signal input, connect to an QFB

CCLK_SEL

Input

LVCMOS

LVCMOS clock reference select

REF_SEL

Input

LVCMOS

LVCMOS/PECL reference clock select

VCO_SEL

Input

LVCMOS

VCO operating frequency select

PLL_EN

Input

LVCMOS

PLL enable/PLL bypass mode select

MR/OE

Input

LVCMOS

Output enable/disable (high-impedance tristate) and device reset

FSEL_A[0:1]

Input

LVCMOS

Frequency divider select for bank A outputs

FSEL_B[0:1]

Input

LVCMOS

Frequency divider select for bank B outputs

FSEL_C[0:1]

Input

LVCMOS

Frequency divider select for bank C outputs

FSEL_FB[0:2]

Input

LVCMOS

Frequency divider select for the QFB output

INV_CLK

Input

LVCMOS

Clock phase selection for outputs QC2 and QC3

STOP_CLK

Input

LVCMOS

Clock input for clock stop circuitry

STOP_DATA

Input

LVCMOS

Configuration data input for clock stop circuitry

QA[0-3]

Output

LVCMOS

Clock outputs (Bank A)

QB[0-3]

Output

LVCMOS

Clock outputs (Bank B)

QC[0-3]

Output

LVCMOS

Clock outputs (Bank C)

QFB

Output

LVCMOS

PLL feedback output. Connect to FB_IN.

QSYNC

Output

LVCMOS

Synchronization pulse output

GND

Supply

Ground

Negative power supply

VCC_PLL

Supply

VCC

PLL positive power supply (analog power supply). It is recommended to use an external RC

filter for the analog power supply pin VCC_PLL. Please see applications section for details.

VCC

Supply

VCC

Positive power supply for I/O and core. All VCC pins must be connected to the positive power

supply for correct operation