REVISION 8 3/16/16

4

©2016 Integrated Device Technology, Inc.

MPC9772 DATA SHEET

Table 2. Function Table (Configuration Controls)

Control

Default

0

1

REF_SEL

1

Selects CCLKx as the PLL reference clock

Selects the crystal oscillator as the PLL

reference clock

CCLK_SEL

1

Selects CCLK0

Selects CCLK1

VCO_SEL

1

Selects VCO

2. The VCO frequency is scaled by a factor of 2 (low VCO

frequency range).

Selects VCO

1. (high VCO frequency range)

PLL_EN

1

Test mode with the PLL bypassed. The reference clock is substituted for the

internal VCO output. MPC9772 is fully static and no minimum frequency

limit applies. All PLL related AC characteristics are not applicable.

Normal operation mode with PLL enabled.

INV_CLK

1

QC2 and QC3 are in phase with QC0 and QC1

QC2 and QC3 are inverted (180

 phase shift)

with respect to QC0 and QC1

MR/OE

1

Outputs disabled (high-impedance state) and device is reset. During

reset/output disable the PLL feedback loop is open and the internal VCO

is tied to its lowest frequency. The MPC9772 requires reset after any loss

of PLL lock. Loss of PLL lock may occur when the external feedback path

is interrupted. The length of the reset pulse should be greater than one

reference clock cycle (CCLKx). The device is reset by the internal power-

on reset (POR) circuitry during power-up.

Outputs enabled (active)

VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency

ratios. See Table 3 to Table 6 and the Applications Information for supported frequency ranges and output to input frequency ratios.

Table 3. Output Divider Bank A (NA)

VCO_SEL

FSEL_A1

FSEL_A0

QA[0:3]

0

0

0

VCO

8

0

0

1

VCO

12

0

1

0

VCO

16

0

1

1

VCO

24

1

0

0

VCO

4

1

0

1

VCO

6

1

1

0

VCO

8

1

1

1

VCO

12

Table 4. Output Divider Bank B (NB)

VCO_SEL

FSEL_B1

FSEL_B0

QB[0:3]

0

0

0

VCO

8

0

0

1

VCO

12

0

1

0

VCO

16

0

1

1

VCO

20

1

0

0

VCO

4

1

0

1

VCO

6

1

1

0

VCO

8

1

1

1

VCO

10

Table 5. Output Divider Bank C (NC)

VCO_SEL

FSEL_C1

FSEL_C0

QC[0:3]

0

0

0

VCO

4

0

0

1

VCO

8

0

1

0

VCO

12

0

1

1

VCO

16

1

0

0

VCO

2