MPC9773 REVISION 6 MARCH 16, 2016

4

©2016 Integrated Device Technology, Inc.

MPC9773 Data Sheet

3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR

VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency

ratios. See Table 3 to Table 6 and the Applications Section for supported frequency ranges and output to input frequency ratios.

Table 2. Function Table (Configuration Controls)

Control

Default

0

1

Table 3. Output Divider Bank A (NA)

VCO_SEL

FSEL_A1

FSEL_A0

QA[0:3]

0

0

0

VCO

8

0

0

1

VCO

12

0

1

0

VCO

16

0

1

1

VCO

24

1

0

0

VCO

4

1

0

1

VCO

6

1

1

0

VCO

8

1

1

1

VCO

12

Table 4. Output Divider Bank B (NB)

VCO_SEL

FSEL_B1

FSEL_B0

QB[0:3]

0

0

0

VCO

8

0

0

1

VCO

12

0

1

0

VCO

16

0

1

1

VCO

20

1

0

0

VCO

4

1

0

1

VCO

6

1

1

0

VCO

8

1

1

1

VCO

10

Table 5. Ouput Divider Bank C (NC)

VCO_SEL

FSEL_C1

FSEL_C0

QC[0:3]

0

0

0

VCO

4

0

0

1

VCO

8

0

1

0

VCO

12

0

1

1

VCO

16

1

0

0

VCO

2

1

0

1

VCO

4

1

1

0

VCO

6

1

1

1

VCO

8

Table 6. Output Divider PLL Feedback (M)

VCO_SEL

FSEL_FB2

FSEL_FB1

FSEL_FB0

QFB

0

0

0

0

VCO

8

0

0

0

1

VCO

12

0

0

1

0

VCO

16

0

0

1

1

VCO

20

0

1

0

0

VCO

16

0

1

0

1

VCO

24

0

1

1

0

VCO

32

0

1

1

1

VCO

40

1

0

0

0

VCO

4

1

0

0

1

VCO

6

1

0

1

0

VCO

8

1

0

1

1

VCO

10

1

1

0

0

VCO

8

1

1

0

1

VCO

12

1

1

1

0

VCO

16