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MPC9773 Datasheet(PDF) 8 Page - Renesas Technology Corp

Part # MPC9773
Description  3.3 V 1:12 LVCMOS PLL Clock Generator
PDF  22 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

MPC9773 Datasheet(HTML) 8 Page - Renesas Technology Corp

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MPC9773 REVISION 6 MARCH 16, 2016
8
©2016 Integrated Device Technology, Inc.
MPC9773 Data Sheet
3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR
BW
PLL Closed Loop Bandwidth(12)
4 feedback
6 feedback
8 feedback
10 feedback
12 feedback
16 feedback
20 feedback
24 feedback
32 feedback
40 feedback
1.20 – 3.50
0.70 – 2.50
0.50 – 1.80
0.45 – 1.20
0.30 – 1.00
0.25 – 0.70
0.20 – 0.55
0.17 – 0.40
0.12 – 0.30
0.11 – 0.28
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
tLOCK
Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50
 to V
TT.
2. The input reference frequency must match the VCO lock range divided by the feedback divider ratio: fREF = fVCO  (M  VCO_SEL).
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
4. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN  fREF  100% and DCREF,MAX = 100% – DCREF,MIN.
5. The MPC9773 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), tPW,MIN, DC and fMAX can only
be guaranteed if tR, tF are within the specified range.
6. CCLKx or PCLK to FB_IN. Static phase offset depends on the reference frequency. t() [s] = t() []  (fREF  360).
7. Excluding QSYNC output. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation.
8. Output duty cycle is DC = (0.5
 200 ps  f
OUT)
 100%. E.g., the DC range at fOUT = 100 MHz is 48% < DC < 52%. T = output period.
9. Cycle jitter is valid for all outputs in the same divider configuration.
10. Period jitter is valid for all outputs in the same divider configuration.
11. I/O jitter is valid for a VCO frequency of 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter vs. VCO frequency.
12. –3 dB point of PLL transfer characteristics.
Table 10. AC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to 85°C)
(1), (2)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition



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