MPC9824 Data Sheet

CLOCK GENERATOR FOR POWERQUICC AND POWERPC MICROPROCESSORS AND MICROCONTROLLERS

MPC9824 REVISION 2 3/16/16

2

©2016 Integrated Device Technology, Inc.

Figure 1. MPC9824 Logic Diagram

Table 1. Pin configuration

Pin

I/O

Type

Function

QA0, QA1, QA2

QA3, QA4, QA5

Output

LVCMOS

Clock Outputs

QREF0, QREF1,

QREF2

Output

LVCMOS

Reference Output (25 MHz)

XTAL_IN

Input

LVCMOS

Crystal Oscillator Input Pin

XTAL_OUT

Output

LVCMOS

Crystal Oscillator Output Pin

REF_IN

Input

LVCMOS

External Reference Input (internal pull-down)

SEL_XTAL

Input

LVCMOS

Selects between XTAL or External Source (internal pull-up)

FSEL0

FSEL1

FSEL2

Input

LVCMOS

Configures Bank A Clock Output Frequency (internal pull-up)

BYPASS

Input

LVCMOS

Test Mode to Bypass PLL (active low, internal pull-up)

MR/OE

Input

LVCMOS

Master Reset (internal pull-down)

VDDA

Analog Supply, An external filter is recommended

VDD

—

—

3.3 V Supply

GND

—

—

Ground

Ref

PLL

QA0

QA1

QA2

QA4

XTAL_IN

OSC

XTAL_OUT

FSEL0

QREF0

FSEL1

QA3

QREF1

QREF2

Data

Generator

MR/OE

200, 33.33, 50,

MHz

25 MHz

or

400 MHz

500 MHz

FSEL2

125,133.33,166.66,

REF_IN

SEL_XTAL

1

0

BYPASS

1

0

QA5

66.66,100