AND8020D datasheet(4/18 Pages) AD

4 / 18 page

AND8020/D

http://onsemi.com

SECTION 1. UNTERMINATED LINES

From transmission line theory, when the driver RE

develops a

DV swing, the signal propagates from point A

arriving at point B at time Td later as shown in Figure 3. This

configuration is also referred to as a stub or an open line.

Figure 3. Unterminated Transmission Line Stub

VEE

T−Line Z0

At point B, the signal is reflected as a function of

òL. If the

input impedance of the receiving gate is large relative to the

line characteristic impedance, according to Equation 4:

òL +

(RL * Z0)

(RL ) Z0)

(eq. 4)

Where:

òL = Load Reflection Coefficient

RL = Load Impedance

Z0 = Line Characteristic Impedance

A large positive reflection occurs resulting in overshoot.

The reflected signal reaches point A at time 2Td , and a large

negative reflection results because the output impedance of

the driver gate is much less than the line characteristic

impedance (i.e. RO << Z0 ).

When the reflected signal arrives at the source it is

reflected back toward the load with a magnitude dictated by

the source reflection coefficient:

òS +

(Rs * Z0)

(Rs ) Z0)

(eq. 5)

Where:

òS = Source Reflection Coefficient

RL = Source Impedance

Z0 = Line Characteristic Impedance

The reflected signal continues to be reflected by the source

and load impedances and is attenuated with each passage over

the transmission line. The output response appears as a

damped oscillation asymptotically approaching a steady state

value. This phenomena is often referred to as “ringing.”

The importance of minimizing the reflected signals lies in

their adverse affect on noise margin and the potential for

driving the input transistors of the succeeding stage into

saturation. Both of these phenomena can lead to less than

ideal system performance. To maximize signal integrity on

transmission lines, four basic techniques are available:

1. Minimizing Interconnect Line Lengths (Section 1)

2. Parallel Termination (Sections 2 and 3)

3. Series Termination (Section 4)

4. Diode Termination (Section 5)

Interconnect Line Lengths

The output signal Waveform rise (tr) and fall (tf) time are

measured from the 20% and 80% levels of the static signal

levels. This edge rate represents the waveforms highest

harmonic and determines the maximum unterminated open

line trace length, Lmax, permissible without sustaining

signal reflections.

The impetus in restricting interconnect lengths, L, is to

mitigate the effects of overshoot and undershoot. A handy

rule of thumb is that the undershoot can be limited to less

than 15% of the logic swing if the two way line delay is less

than the rise time of the pulse. With an undershoot of <15%,

the physics of the situation will result in an overshoot which

will not cause saturation problems at the receiving input.

Thus, the maximum line length can be determined:

L max t

2*Tpd

(eq. 6)

Where:

Lmax = Maximum Open Line Length

tr = Signal Rise Time

Tpd = Length Pulse Delay per Unit Length

Further, the propagation delay increases with gate

loading; thus, the effective delay per unit length (TpdEff) is

given as:

TpdEff + Tpd

)

L*CO

(eq. 7)

Where:

Tpd = Length Pulse Delay per Unit Length

CD = Distributed Capacitance

CO = Capacitance per Unit Length (Foot)

L = Line Length

Using the effective delay per unit length, TpdEff, yields:

tr y (2) (L) (Tpd )

)

L*CO

(eq. 8)

Solving for Lmax line length produces:

L max + 0.5

)

tpd

(eq. 9)

Where:

Lmax = Line Length Maximum

CD = Distributed Capacitance

CO = Capacitance per Unit Length (Foot)

Tpd = Length Pulse Delay per Unit Length

Assuming a worst case capacitance of 2 pF and a rise time

of 100 ps for EP gives a value of 0.03 inch for the maximum

open line length. Maximum open line lengths derived from

SPICE simulations for single and double gate loads, a

maximum overshoot of 40% and undershoot of 20% was

assumed. The simulation results indicate that for a 50

W line,

a stub length of

x 0.03 inches will limit the overshoot to less

than 40%, and the undershoot to within 20% of the logic

swing. Signal traces will most assuredly be larger than

0.03 inch for most practical applications.

Therefore, it will be necessary to use controlled

impedance environments for EP devices in general and

devices with faster edges.

AND8020D Datasheet(PDF) 4 Page - Analog Devices

AND8020D Datasheet(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL