ZLED7001 Datasheet

© 2016 Integrated Device Technology, Inc.

12

April 20, 2016

4

Pin Configuration and Package

Figure 4.1

Pin Configuration ZLED7001

VIN

TOFF

CS

GATE

GND

LD

PWMD

VREF

Table 4.1

Pin Description SOP-8

Pin Name

NO.

Description

VREF

1

1.2V reference voltage. No bypass capacitor needed.

PWMD

2

PWM dimming input. The gate driver operates normally if PWMD is pulled high. The gate driver is turned

off if PWMD is pulled to GND or open.

LD

3

Linear dimming input. If the voltage at LD is < 240mV (typical), LD controls the current sense threshold.

Can also be used as temperature compensation threshold voltage.

GND

4

Internal circuit ground reference. Electrical connection to ground is required.

GATE

5

Output for external N-channel power MOSFET gate driver.

CS

6

Current sense pin that senses the Q1 MOSFET drain current through external resistor RCS. The GATE

output goes low if the voltage at CS > the voltage at the LD pin or the internal 240mV.

TOFF

7

Sets the off-time of the power MOSFET. If left floating, off-time will be 510ns. For increased off-time, a

capacitor must be connected between TOFF and GND.

VIN

8

Supply input of 8V to 450V through a resistor, clamped at 7.1V internally. Low-ESR bypass capacitor to

GND is required.