ZOPT2201 Datasheet

© 2016 Integrated Device Technology, Inc

23

September 2, 2016

The threshold interrupt is enabled with LS_INT_EN = 1 and LS_VAR_MODE = 0. The interrupt is set when the respective *_DATA register

value of the selected interrupt source channel is above the upper or below the lower threshold configured in the LS_THRES_UP and

LS_THRES_LOW registers (see sections 3.11.12 and 3.11.13 respectively) for a specified number of consecutive measurements as

configured in the INT_PST register (1 + LS_PERSIST; see section 3.11.11).

The variance interrupt is enabled with LS_INT_EN = 1 and LS_VAR_MODE = 1. It is set when the absolute value difference between the

preceding and the current output data of the selected interrupt source channel is above the decoded variance threshold (see section 3.11.14)

for a specified number of consecutive measurements (1 + LS_PERSIST).

3.9

I²C Interface

The ZOPT2201 is equipped with an I²C interface for control and data communication. The chip always operates as a slave. The device offers

two different 7-bit slave addresses that are selectable via NVM programming. A read/write bit must be appended to the slave address by the

master device to properly communicate with the device.

The interface is compatible with standard mode (100kHz) and fast mode (400kHz) I²C communication.

Table 3.7 Supported I²C Clock Frequencies

Mode

Frequency

Transient Noise Filter

Standard

100kHz

50ns

Fast

400kHz

50ns

The I²C circuitry is always active (Standby or Active Mode of the ZOPT2201). If the I²C address is not yet read from the memory block, the

device will respond with “NACK” to any request and ignore the possible commands. An attempt to read or write to non-existing addresses will

be answered with “NACK.”

3.9.1

I²C Address Decoding

The I²C address decoding is done during start up after a power-on-reset or software reset. Two different I²C addresses can be selected

through NVM programming (see Table 3.8).

Table 3.8 I²C Address

Address NVM Level

I²C Address

7 Bits

Write

Read

0 – Default

1010 011xBIN

A6HEX

A7HEX

1 – Programmed

1010 010xBIN

A4HEX

A5HEX

3.9.2

I²C Register Read

The ZOPT2201 registers can be read individually or in block read mode. When two or more bytes are read in block read mode, reserved

register addresses are skipped and the next valid address is referenced. If the last valid address has been reached, but the master continues

with the block read, the address counter in the ZOPT2201 will not roll over and the ZOPT2201 returns 00HEX for every subsequent byte read.

The block read operation is the only way to ensure correct data read out of multi-byte registers and to avoid splitting of results with HIGH and

LOW bytes originating from different conversions. During block read access on LS result registers, the result update is blocked.

If a read access is started on an address belonging to a non-readable register, the ZOPT2201 will return NACK until the I2C operation is

ended.

Read operations must follow the timing diagram in Figure 3.6.