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TL16C752BTPTREP Datasheet(PDF) 17 Page - Texas Instruments |
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TL16C752BTPTREP Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 35 page  TL16C752B-EP 3.3-V DUAL UART WITH 64-BYTE FIFO SGLS153 – FEBRUARY 2003 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements TA = –40°C to 110°C, VCC = 3.3 V ± 10% (unless otherwise noted) (see Figures 12–19) PARAMETER TEST CONDITIONS MIN MAX UNIT td1 IOR delay from chip select 0 ns td2 Read cycle delay 2tp(I)‡ ns td3 Delay from IOR to data 28.5 ns td4 Data disable time 15 ns td5 IOW delay from chip select 10 ns td6 Write cycle delay 2tp(I)‡ ns td7 Delay from IOW to output 100-pF load 50 ns td8 Delay to set interrupt from MODEM input 100-pF load 70 ns td9 Delay to reset interrupt from IOR 100-pF load 70 ns td10 Delay from stop to set interrupt 1Rclk † td11 Delay from IOR to reset interrupt 100-pF load 70 ns td12 Delay from stop to interrupt 100 ns td13 Delay from initial INT reset to transmit start 8 24 † td14 Delay from IOW to reset interrupt 70 ns td15 Delay from stop to set RXRDY 1 Clock td16 Delay from IOR to reset RXRDY 1 µs td17 Delay from IOW to set TXRDY 70 ns td18 Delay from start to reset TXRDY 16 † td19 Delay between successive assertion of IOW and IOR 4P‡ † th1 Chip select hold time from IOR 0 ns th2 Chip select hold time from IOW 0 ns th3 Data hold time 15 ns th4 Address hold time 0 ns th5 Hold time from XTAL1 clock ↓ to IOW or IOR release 20 ns tp1, tp2 Clock cycle period 20 ns tp3 Oscillator/clock speed VCC = 3 V 48 MHz t(RESET) Reset pulse width 200 ns tsu1 Address setup time 0 ns tsu2 Data setup time 16 ns tsu3 Setup time from IOW or IOR assertion to XTAL1 clock ↑ 20 ns tw1 IOR strobe width 2tp(I)‡ ns tw2 IOW strobe width§ 2tp(I)‡ ns † Baud rate ‡ tp(I) = input clock period |
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