ADAV400 datasheet(33/36 Pages) AD

33 / 36 page

ADAV400

Rev. 0 | Page 33 of 36

Table 27 can also be used to verify register settings for each

serial data format.

SRC SERIAL PORT CONTROL REGISTER

SRC Serial Input Port Select (Bits [6:5])

These bits select which of the four serial data inputs are directed

to the SRC

LRCLK Polarity (Bit 4)

When this bit is set to 0, the left channel data on the selected

channel is clocked in when LRCLK0 is low, and the right

channel input data is clocked in when LRCLK1 is high. When

this bit is set to 1, this sequence is reversed.

BCLK Polarity (Bit 3)

This bit controls on which edge of the bit clock the input data

changes, and on which edge it is clocked. Data changes on the

falling edge of BCLK0 when this bit is set to 0, and on the rising

edge when this bit is set to 1.

Serial Input Mode (Bits [2:0])

These two bits control the data format that the input port expects

to receive. It should be noted that Bit 3 and Bit 4 of the serial input

control register will override these settings, so Bits 4 to Bit 0

must be set for correct operation. Refer to Figure 31, Figure 32,

Figure 33, and Figure 34 for details on the different modes.

Table 27 can also be used to verify register settings for each

serial data format.

Note that TDM is not supported on the SRC.

ADC INPUT MUX REGISTER

ADC Input Mux (Bits [3:0])

These bits are used to select which of the analog inputs are

directed to the ADC. It is recommended that only one channel

is selected at any time.

POWER CONTROL REGISTER

Power Control (Bits [15:0])

These bits can individually power up or power down the

different blocks of the ADAV400.

USER CONTROL REGISTER 2

Headphone Amplifier Mute (Bit 7)

When set, this bit mutes the analog headphone amplifier.

Headphone Amplifier Attenuation (Bits [4:0])

These bits set the analog gain of the headphone amplifier. It can

be set in steps of −1.5 dB from 0 dB to −46.5 dB.

USER CONTROL REGISTER 1

SRC Mux Enable (Bit 8)

When this bit is set to 1, the SRC mux is enabled, passing the

input selected by the SRC serial port control register to the SRC

block, the output of which is then available to the DSP core. It

also masks the selected serial data input as a direct input to the

DSP core. See Figure 36 for more details on the SRC input

configuration.

AUDIO

PROCESSOR

CORE

MULTICHANNEL

DIGITAL INPUTS

SDIN0

SRC

REG: 0x1058

BIT 2

REG: 0x1056

BITS [6:5]

SDIN1

LRCLK0

BCLK0

SDIN2

SDIN3

Figure 36. SRC Input Configuration

SRC Lock Indicator (Bit 7)

This bit is read only and indicates when the SRC is locked.

MCLKO Pin Enable (Bit 6)

With this bit set to 1, MCLKO is enabled and outputs the

frequency selected by Bit 5 to Bit 3 in this register.

MCLKO Select (Bits [5:3])

These bits select the MCLKO frequency. All reserved settings

are test modes and are not valid audio clocks.

PLL Clock Select (Bits [2:0])

These bits must be programmed to select the master clock,

MCLKI, input frequency that is being used. For example, the

default case is 64 × fS (3.072 MHz), which means that BCLKx

can also be used as the MCLKI.

DAC AMPLIFIER REGISTER

DAC Amplifier Chopping (Bit 4)

This bit should be set to 1 to ensure best performance on the

headphone outputs.

ADAV400 Datasheet(PDF) 33 Page - Analog Devices

ADAV400 Datasheet(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL