LT4256-2CS8 datasheet(13/16 Pages) LINER

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LT4256-1/LT4256-2

425612f

Figure 13.

∆VGATE vs VCC

Supply Transient Protection

The LT4256-1/LT4256-2 is 100% tested and guaranteed

to be safe from damage with supply voltages up to 80V.

However, voltage transients above 100V may cause per-

manent damage. During a short-circuit condition, the

large change in currents flowing through the power supply

traces can cause inductive voltage transients which could

exceed 100V. To minimize the voltage transients, the

power trace parasitic inductance should be minimized by

using wider traces or heavier trace plating and a 0.1

µF

bypass capacitor should be placed between VCC and GND.

A surge suppressor, as shown in the application diagrams,

(Transzorb) at the input can also prevent damage from

voltage transients.

GATE Pin

A curve of gate drive vs VCC is shown in Figure 13. GATE

is clamped to a maximum voltage of 12.8V above VCC. This

clamp is designed to sink the internal charge pump cur-

rent. An external Zener diode must be used as shown in all

applications. At a minimum input supply voltage of 12V,

the minimum gate drive voltage is 4.5V. When the input

supply voltage is higher than 20V, the gate drive voltage is

at least 10V and a standard threshold MOSFET can be

used. In applications from 12V to 15V range, a logic level

MOSFET must be used.

In some applications it may be possible for the VOUT pin to

ring below ground (due to the parasitic trace inductance).

VCC (V)

4256 F13

APPLICATIO S I FOR ATIO

Higher current applications, especially where the output

load is physically far away from the LT4256-1/LT4256-2

will be more susceptible to these transients. This is normal

and the LT4256-1/LT4256-2 have been designed to allow

for some ringing below ground. However, if the applica-

tion is such that VOUT can ring more than 10V below

ground, damage may occur to the LT4256-1 and an

external diode from ground (anode) to VOUT (cathode)

must be added to the circuit as shown in Figure 14 (it is

critical that the reverse breakdown voltage of the diode be

higher than the highest expected VCC voltage). A capacitor

placed from ground to VOUT directly at the LT4256-1/

LT4256-2 can help reduce the amount of ringing on VOUT

but it may not be enough for some applications.

During a fault condition, the LT4256-1/LT4256-2 pulls

down on GATE with a switch capable of sinking about

60mA. Once GATE drops below the output voltage by a

diode forward voltage, the external Zener will forward bias

and VOUT will also be discharged to GND. In addition to the

GATE capacitance, the output capacitance will be dis-

charged through the LT4256-1/LT4256-2.

In applications utilizing very large external N-channel

MOSFETs, the possibility exists for the MOSFET to turn on

when initially inserted into a live backplane (before the

LT4256-1/LT4256-2 becomes active and pulls down on

GATE). This is due to the drain to gate capacitance forcing

current into R7 and C1 when the drain voltage steps up

from ground to VIN with an extremely fast rise time. To

alleviate this situation, a diode, D3, should be put

across R7 with the cathode connected to C1 as shown in

Figure 15.

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