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DP83849C Datasheet(PDF) 49 Page - National Semiconductor (TI) |
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DP83849C Datasheet(HTML) 49 Page - National Semiconductor (TI) |
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49 / 96 page ![]() 49 www.national.com 7 COLLISION TEST 0, RW Collision Test: 1 = Collision test enabled. 0 = Normal operation. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN within 512-bit times. The COL signal will be de-asserted within 4-bit times in response to the de-assertion of TX_EN. 6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0. Table 20. Basic Mode Control Register (BMCR), address 00h (Continued) Bit Bit Name Default Description |
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