ICS9LRS3187B datasheet(2/21 Pages) RENESAS

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IDT® Programmable Timing Control Hub for Intel Based Systems

1602F—11/04/11

ICS9LRS3187B

Programmable Timing Control Hub for Intel Based Systems

Datasheet

Pin Description

Pin# Pin Name

Type Pin Description

VDDDOT96MHz_3.3

PWR Power pin for the 96MHz output 3.3V.

GNDDOT96MHz

PWR Ground pin for the 96MHz output

DOT96T_LPR

OUT

True DOT96 output with integrated 33ohm series resistor. No

50ohm resistor to GND needed.

DOT96C_LPR

OUT

Complement DOT96 output with integrated 33ohm series

resistor. No 50ohm resistor to GND needed.

VDD_27MHz

PWR Power pin for the 27MHz output 3.3V.

27MHz_nonSS

OUT

3.3V Single-ended 27MHz non-spread clock.

27MHz_SS

OUT

3.3V Single-ended 27MHz spread clock.

GND27MHz

OUT

Ground pin for the 27MHz outputs.

GNDSATA

PWR Ground pin for the SATA outputs.

SATAT_LPR

OUT

True clock of differential 0.8V push-pull SATA/SRC output with

integrated 33ohm series resistor. No 50ohm resistor to GND

needed.

SATAC_LPR

OUT

Complementary clock of differential 0.8V push-pull SATA/SRC

output with integrated 33ohm series resistor. No 50ohm resistor

to GND needed.

GNDSRC

PWR Ground pin for the SRC outputs

SRCT1_LPR

OUT

True clock of differential 0.8V push-pull SRC output with

integrated 33ohm series resistor. No 50ohm resistor to GND

needed.

SRCC1_LPR

OUT

Complementary clock of differential 0.8V push-pull SRC output

with integrated 33ohm series resistor. No 50ohm resistor to

GND needed.

VDDSRC_IO

PWR 1.05V to 3.3V from external power supply

*CPU_STOP#

Stops all CPU clocks, except those set to be free running

clocks

VDDSRC_3.3

PWR Supply for SRC clocks, 3.3V nominal

VDDCPU_IO

PWR 1.05V to 3.3V from external power supply

CPUC1_LPR

OUT

Complementary clock of differential pair 0.8V push-pull CPU

outputs with integrated 33ohm series resistor. No 50 ohm

resistor to GND needed.

CPUT1_LPR

OUT

True clock of differential pair 0.8V push-pull CPU outputs with

integrated 33ohm series resistor. No 50 ohm resistor to GND

needed.

GNDCPU

PWR Ground pin for the CPU outputs.

CPUC0_LPR

OUT

Complementary clock of differential pair 0.8V push-pull CPU

outputs with integrated 33ohm series resistor. No 50 ohm

resistor to GND needed.

CPUT0_LPR

OUT

True clock of differential pair 0.8V push-pull CPU outputs with

integrated 33ohm series resistor. No 50 ohm resistor to GND

needed.

VDDCPU_3.3

PWR Supply for CPU clocks, 3.3V nominal

CLKPWRGD/PD#_3.3

Notifies CK505 to sample latched inputs, or PWRDWN# mode

GNDREF

PWR Ground pin for the REF outputs.

OUT

Crystal output, Nominally 14.318MHz

Crystal input, Nominally 14.318MHz

VDDREF_3.3

PWR Power pin for the XTAL and REF clocks, nominal 3.3V

REF_2/FSLC_3.3**

I/O

14.318 MHz reference clock, which can drive 2 loads / 3.3V

tolerant input for CPU frequency selection. Refer to input

electrical characteristics for Vil_FS and Vih_FS values.

SDATA_3.3

I/O

Data pin for SMBus circuitry, 3.3V tolerant

SCLK_3.3

Clock pin of SMBus circuitry, 3.3V tolerant.

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