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CYT4DNJBJS Datasheet(PDF) 146 Page - Infineon Technologies AG |
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CYT4DNJBJS Datasheet(HTML) 146 Page - Infineon Technologies AG |
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146 / 209 page  Datasheet 146 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Electrical specifications SID583 VTR_5P5_F High-voltage OVD 5.5-V trimmed falling trip point for VDDD and VDDA_ADC (default) 5.524 5.695 5.866 V SID585 HVOVD_RR_A Power ramp rate: VDDD and VDDA_ADC (Active) –– 100 mV/µs SID586 HVOVD_RR_DS Power ramp rate: VDDD and VDDA_ADC (DeepSleep) –– 10 mV/µs SID587 tDLY_ACT_HVOVD Active mode delay between VDDD falling/rising through VTR_5P0_F/R or VTR_5P5_F/R and an internal HV OVD output transitioning through VDDD / 2 –– 1µs Guaranteed by design SID587A tDLY_ACT_H- VOVD_A Active mode delay between VDDA_ADC falling/rising through VTR_5P0_F/R or VTR_5P5_F/R and an internal HV OVD output transitioning through VDDD / 2 –– 1.5 µs Guaranteed by design SID587B tDLY_DS_HVOVD DeepSleep mode delay between VDDD/VDDA_ADC falling/rising through VTR_5P0_F/R or VTR_5P5_F/R and an internal HV OVD output transitioning through VDDD / 2 –– 4µs Guaranteed by design SID588 tRES_HVOVD Response time of HV OVD HV OVD guaranteed to generate pulse for VDDD/VDDA_ADC pulse width greater than this. (For rising-then-falling supply at max ramp rate; pulse width is time above VTR_5P0_R or VTR_5P5_R) 100 – – ns Guaranteed by design Low-voltage OVD specifications SID590 VTR_R_LVOVD LV OVD trimmed rising trip point for VCCD Typ – 3% 1300 Typ + 3% mV SID591 VTR_F_LVOVD LV OVD trimmed falling trip point for VCCD Typ – 3% 1275 Typ + 3% mV Same as VTR_R_LVOVD – 25 mV SID595 tDLY_ACT_LVOVD Active mode delay between VCCD falling/rising through VTR_F/R_LVOVD and an internal LV OVD output transi- tioning through VDDD / 2 –– 1µs Guaranteed by design SID595A tDLY_DS_LVOVD DeepSleepmodedelaybetweenVCCD falling/rising through VTR_F/R_LVOVD and an internal LV OVD output transi- tioning through VDDD / 2 –– 12 µs Guaranteed by design SID596 tRES_LVOVD Response time of LV OVD. LV OVD guaranteed to generate pulse for VCCD pulse width greater than this. (For rising-then-falling supply at max ramp rate; pulse width is time above VTR_R_LVOVD) 100 – – ns Guaranteed by design Over current detection (OCD) specifications SID598 IOCD Over current detection range for internal Active regulator 312 – 630 mA Guaranteed by design SID599 IOCD_DPSLP Over current detection range for internal DeepSleep regulator 18 – 72 mA Table 26-15 System resources (continued) Spec ID Parameter Description Min Typ Max Units Details/ conditions |
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