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CYT4DNJBJS Datasheet(PDF) 165 Page - Infineon Technologies AG |
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CYT4DNJBJS Datasheet(HTML) 165 Page - Infineon Technologies AG |
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165 / 209 page  Datasheet 165 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Electrical specifications Figure 26-29 RGMII Rx timing diagram 26.11.1 Minimum bus frequency requirements The following table details the required minimum operating frequencies for all possible Ethernet configurations and MAC speeds. Ethernet module uses AXI interface for DMA access. Table 26-32 Minimum AXI frequency for MAC speeds DMA bus width MAC rate Minimum AXI frequency 64 1 Gbps 65 MHz 64 100 Mbps 10 MHz 64 10 Mbps 10 MHz 1 RX_CLK, TX_CLK TX_CTL, RX_CTL, TXD, RXD 1: TX_CLK and RX_CLK clock cycle = 1/fCYC 2: Data to clock input skew = tSKEWR 100 % 50 % 0 % 100 % 50 % 0 % 22 2 2 |
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