CYT3DLABFS datasheet(7/207 Pages) INFINEON

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Datasheet

7 of 207

002-27763 Rev.*H

2023-03-03

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 single

Features list

1Features list

Table 1-1

CYT3DL feature list

Features

Packages

216-TEQFP

272-BGA

CPU

Core

32-bit Arm® Cortex®-M7 CPU and 32-bit Arm® Cortex®-M0+ CPU

Functional safety

ASIL-B

Operation voltage for GPIO_STD

2.7V to 5.5V

Operation voltage for GPIO_ENH

2.7V to 5.5V

Operation voltage for GPIO_SMC

2.7V to 5.5V

Operation voltage for HSIO_STDLN

3.0 V to 3.6 V

Core voltage VCCD

1.09 V to 1.21 V

Operation frequency

Arm® Cortex®-M7 240 MHz (max) and Arm® Cortex®-M0+ 100 MHz (max)

MPU, PPU

Supported

FPU

Supports both single (32-bit) and double (64-bit) precision

DSP-MUL/DIV/MAC

Supported by Arm® Cortex®-M7 CPU

TCM

64-KB instruction and 64-KB data for Cortex®-M7 CPU

Memory

Code-flash

4160 KB (4031 KB + 128 KB)

Work-flash

128 KB (96 KB + 32 KB)

SRAM (configurable for retention)

384 KB

ROM

64 KB

Communication Interfaces

CAN0 (CAN-FD: Up to 8 Mbps)

2 ch

CAN1 (CAN-FD: Up to 8 Mbps)

2 ch

CAN RAM

16 KB per instance (2 ch), 32 KB in total

Serial Communication Block (SCB/UART)

9 ch

12 ch

Serial Communication Block (SCB/I2C)

9 ch

11 ch

Serial Communication Block (SCB/SPI)

8 ch

11 ch

LIN0

2 ch

CXPI controller

2 ch

Ethernet MAC

1 ch × 10/100

Memory Interfaces

SMIF (Single SPI / Dual SPI / Quad SPI / Octal SPI / xSPI)

2 ch (HSIO_STDLN at 100 MHz)

2 ch (HSIO_STDLN at 133 MHz)

Timers

RTC

1 ch

TCPWM (16-bit)

38 ch

TCPWM (16-bit) SMC

12 ch (Equivalent to 6 ch SMC with ZPD and slew rate control)

TCPWM (32-bit)

32 ch

External Interrupts

108

135

Analog

12-bit, 1 Msps SAR ADC

1 Unit (SAR#0, 32 logical channels)

48 external channels

6 ch for Internal sampling

Security

Flash Security (program/work read protection)

Supported

CYT3DLABFS Datasheet(PDF) 7 Page - Infineon Technologies AG

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