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PIC24FJ64GA006 Datasheet(PDF) 74 Page - Microchip Technology |
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PIC24FJ64GA006 Datasheet(HTML) 74 Page - Microchip Technology |
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74 / 232 page ![]() PIC24FJ128GA FAMILY DS39747C-page 72 Preliminary © 2006 Microchip Technology Inc. REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 Upper Byte: U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 —RTCIE — — — — — — bit 15 bit 8 Lower Byte: U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IE INT3IE — — MI2C2IE SI2C2IE — bit 7 bit 0 bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13-7 Unimplemented: Read as ‘0’ bit 6 INT4IE: External Interrupt 4 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 INT3IE: External Interrupt 3 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ . Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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