10 Functional Description

The CDL Transceiver consists of nine major functional

blocks as shown in

Figure 1 The Transmit section includes

the following the Delay Line the Delay Line Calibrator the

Media Format Logic and the Current Output Driver circuitry

with its bias circuitry The Delay Line accepts the NRZI en-

‘‘memory’’ of the bit that preceded the bit currently being

transmitted The Delay Line Calibrator allows the use of an

external resistor which governs the time calibration of the

delay line The Delay Line outputs the data via taps which

are tied to the Media Format Logic The encoding logic is

dependent on the state of the Media Select pin The encod-

ed data is routed to the Current Output Driver through the

The Receive section consists of the following a differential

input amplifier Signal Detect circuitry a Loopback Multi-

plexer and differential 100K output drivers for data and Sig-

from the receive isolation transformer The input signal is

sensed by the Signal Detect circuit The input signal also

drives a differential input amplifier whose output is coupled

to the Loopback Mux logic The ‘sel’ input which is driven by

is routed to the differential 100K Output Driver When in

Loopback mode the Signal Detect output driver is forced

true When receiving data from copper media the signal

detect circuit provides valid states to the Signal Detect out-

put driver depending on the amplitude of the incoming sig-

Detect is the final gating function for data reception If no

media is detected the transceiver will generate a logic low

Signal Detect which will inhibit data reception by the PHY

11 SDDI OPERATION

The CDL allows full compatibility with the current SDDI

specification By allowing the MSEL pin to float which

tion is selected The appropriate transmit voltage amplitude

must also be set by selecting a value of 26 kX for the

TXREF resistor

Finally it is important to note that the CDL must be used in

conjunction with the Pulse Engineering 83 magnetics mod-

ule in order to conform to the current SDDI specification No

special terminations are required in connecting the Pulse

Engineering 83 module to the CDL (Refer to the typical

SDDI schematic

Figure 9 )

20 Pinout Summary

Signal

Pin No

Description

Type

13 26

Supply

GND

14 22

GND

Supply

4 27

Supply

RXGND

3 28

Receive GND

Supply

5 11

Supply

TXGND

7 10

Transmit GND

Supply

23

Supply

2 1

Receive Data Inputs

Current In

25 24

Physical Media Indicate Data

ECL Out

15 16

Physical Media Request Data

ECL In

9 8

Transmit Data Outputs

Current Out

20 21

Signal Detect Outputs

ECL Out

TXREF

6

Transmit Amplitude Reference

Current Out

DELREF

12

Delay Line Calibration Reference

Current Out

LBEN

19

Loopback Enable

CMOS In

MSEL

17

Media Select

3-Level Select

CDET

18

Cable Detect Bar

CMOS Schmitt Trigger In

2