30 Pin Definitions

patible circuitry The Transceiver operates from a single

a

GND (1422)

Return path for the 100K ECL compatible cir-

cuitry power supply

receive circuitry This power supply is intentionally separat-

ed from others to eliminate receive errors due to coupled

supply noise

RXGND (328)

Return path for the receive power supply

circuitry This Power supply return is intentionally separated

from others to eliminate receive errors due to coupled sup-

ply noise

portion of the transmit circuitry This power supply is inten-

tionally separated from the others to prevent supply noise

from coupling to the transmit outputs

TXGND (710)

Return path for the analog transmit power

supply circuitry This supply return is intentionally separated

from others to prevent supply noise from being coupled to

the transmit outputs

cuitry

Balanced differential line receiver inputs Sig-

nals meeting the input threshold for a given media type are

100K ECL compatible differential outputs

used as the source of the receive data for the DP83231

Differential 100K compatible 4B5B NRZI

transmit data inputs originating from the DP8325155 Physi-

Differential current driver outputs precompen-

sated for twisted pair cable

Differential 100K ECL compatible Signal De-

tect outputs indicating that a valid signal is present at the

DELREF (12)

A resistor is connected between this pin and

GND The value of this resistor controls the current into the

delay line calibrator which in turn controls the delay time of

the delay line

TXREF (6)

A resistor is connected between this pin and

TXGND The value of this resistor controls the signal ampli-

LBEN (19)

TTL compatible CMOS Loopback Enable input

pin selects the internal loopback path which effectively

MSEL (17)

The Media Select input controls the compensa-

tion and output current required to drive to 100 meters of

either STP or DTP media This is a tri-Ievel control pin

When forced to a low voltage STP compensation is select-

ed Forcing a high voltage level will select the DTP compen-

sation mode Forcing a median voltage allows the device to

operate in the transparent mode by deasserting pre-empha-

sis

CDET (18)

The Cable Detect input is provided to support

the option of external Cable Detection circuitry With CDET

low the CDL transceiver functions normally When CDET is

high the signal detect output is forced low which inhibits

data reception by the PHY The exception is in the case of

Loop Back where Signal Detect is forced high regardless

28-Pin PLCC

TLF11724 – 3

Order Number DP83220V

See NS Package Number V28A

FIGURE 2 Pin Configuration

TLF11724 – 4

FIGURE 3 System Connection Diagram

3