ICS1524AMLF datasheet(11/25 Pages) RENESAS

Part #	ICS1524AMLF

Description	Dual Output Phase Controlled SSTL_3/PECL Clock Generator

PDF	25 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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ICS1524A

ICS1524A Rev F 05/13/10

Name:

Oscillator Divider Register

Index:

Read / Write

Bit Name

Bit #

Reset Value

Description

Osc_Div 0-6

0-6

Osc Divider Modulus

In_Sel

Input Select

Bit

Name

Description

0 - 6

Osc_Div 0-6

Oscillator Divider Modulus.

Divides the input from OSC (pin 12) by the set modulus.

The modulus equals the programmed value, plus 2.

Therefore, the modulus range is from 3 to 129.

In_Sel

Input Select — Selects the input to the Phase/Frequency Detector

0 = HSYNC

1 = Osc Divider

Name:

RESET Register

8 h

Index:

Write

Bit Name

Bit #

Reset Value

Description

DPA Reset

0 -3

Writing xAh to this register resets DPA working register 5

PLL Reset

4 -7

Writing 5xh to this register resets PLL working registers 1-3

Bit

Name

Description

0 - 3

DPA

Writing xAh to this register resets DPA working register 5

4 -7

PLL

Writing 5xh to this register resets PLL working registers 1-3

ICS1524AMLF Datasheet(PDF) 11 Page - Renesas Technology Corp

ICS1524AMLF Datasheet(HTML) 11 Page - Renesas Technology Corp

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