ICS8535-01 DATA SHEET

LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL

FANOUT BUFFER

8

REVISION F 08/11/14

Applications Information

Recommendations for Unused Input Pins

Inputs:

CLK Input

For applications not requiring the use of a clock input, it can be left

floating. Though not required, but for additional protection, a 1k



resistor can be tied from the CLK input to ground.

LVCMOS Control Pins

All control pins have internal pullups; additional resistance is not

required but can be added for additional protection. A 1k

 resistor

can be used.

Outputs:

LVPECL Outputs

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential output is a low impedance follower output that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50



transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figure 2A and Figure 2B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 2A. 3.3V LVPECL Output Termination

Figure 2B. 3.3V LVPECL Output Termination

R1

84



R2

84



3.3V

R3

125



R4

125



o =50

o =50

LVPECL

Input

3.3V

3.3V

+

_