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ICS8535-01 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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ICS8535-01 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 19 page ![]() DATA SHEET Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL Fanout Buffer ICS8535-01 ICS8535-01 REVISION F 08/11/14 1 ©2014 Integrated Device Technology, Inc. General Description The ICS8535-01 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The ICS8535- 01 has two single ended clock inputs. the single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ICS8535-01 ideal for those applications demanding well defined performance and repeatability. 6 7 8 9 10 19 20 18 17 16 1 2 3 4 5 VCC Q2 nQ2 VCC nc 13 14 15 12 11 Q3 nQ3 VCC VEE CLK_EN 1 2 3 4 5 6 7 8 9 10 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3 20 19 18 17 16 15 14 13 12 11 VEE CLK_EN CLK_SEL CLK0 nc CLK1 nc nc nc VCC ICS8535-01 20-Lead VFQFN 4mm x 4mm x 0.9 body package K Package Top View ICS8535-01 20-Lead TSSOP 4.4mm x 6.5mm x 0.92 body package G Package Top View Pin Assignment Features • Four differential 3.3V LVPECL outputs • Selectable CLK0 or CLK1 inputs for redundant and multiple frequency fanout applications • CLK0 or CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 266MHz • Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels • Output skew: 30ps (maximum) • Part-to-part skew: 250ps (maximum) • Propagation delay: 1.9ns (maximum) • Additive phase jitter, RMS: < 0.09ps (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Lead-free (RoHS 6) packaging Block Diagram CLK0 CLK1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 0 1 CLK_EN CLK_SEL D Q LE |
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