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HT36B4 Datasheet(PDF) 4 Page - Holtek Semiconductor Inc

Part # HT36B4
Description  Music Synthesizer 8-Bit MCU
PDF  38 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT36B4 Datasheet(HTML) 4 Page - Holtek Semiconductor Inc

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Absolute Maximum Ratings
Supply Voltage .............................VSS
-0.3V to VSS+6V
Storage Temperature ...........................
-50°Cto125°C
Input Voltage .............................VSS
-0.3V to VDD+0.3V
Operating Temperature ..........................
-40°Cto85°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25
°C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Conditions
VDD
Operating Voltage
¾¾
2.4
3
5
V
IDD
Operating Current
5V
No load,
fOSC=11.0592MHz
¾
816
mA
ISTB
Standby Current (WDT Disabled)
5V
No load, System HALT
¾
0
¾mA
IOL
I/O Ports Sink Current
5V
VOL=0.5V
9.7
16.2
¾
mA
IOH
I/O Ports Source Current
5V
VOH=4.5V
-5.2
-8.7
¾
mA
RPH
Pull-High Resistance of I/O Ports
5V
VIL=0V
11
22
44
k
W
VIH1
Input High Voltage for I/O Ports
5V
¾
3.5
¾
5V
VIL1
Input Low Voltage for I/O Ports
5V
¾
0
¾
1.5
V
VIH2
Input High Voltage (RES)5V
¾¾
4
¾
V
VIL2
Input Low Voltage (RES)5V
¾¾
2.5
¾
V
A.C. Characteristics
Ta=25
°C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Conditions
MCU interface
fOSC
System Frequency
5V
12MHz crystal
¾
12
¾
MHz
fSYS
System Clock
5V
¾
4
¾
16
MHz
tWDT
Watchdog Time-Out Period (RC)
¾
Without WDT prescaler
9
17
35
ms
tRES
External Reset Low Pulse Width
¾¾
1
¾¾
ms
Symbol
Parameter
Figure
Min.
Typ.
Max.
Unit
DAC interface
fBC
DCK Bit Clock Frequency
Fig 1
¾
fSYS/16
¾
MHz
tCH
DCK Bit Clock H Level Time
Fig 1
600
¾¾
ns
tDOS
Data Output Setup Time
Fig 1
200
¾¾
ns
tDOH
Data Output Hold Time
Fig 1
200
¾¾
ns
tLCS
Load Clock Setup Time
Fig 1
200
¾¾
ns
tLCH
Load Clock Hold Time
Fig 1
200
¾¾
ns
HT36B4
Rev. 1.00
4
October 18, 2006



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