TMPR4955AF datasheet(153/168 Pages) TOSHIBA

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Chapter 9 Debug Support Unit

9-1

Chapter 9.

Debug Support Unit

9.1

Features

1. Utilizes JTAG interface compatible with IEEE Std. 1149.1.

2. Processor access to external processor probe to execute from the external trace memory during

debug exception and boot time. This is to eliminate system memory for debugging purpose.

3. Supports DMA access through JTAG interface to internal processor bus to access internal

registers, host system peripherals and system memory.

4. Debug functions

• Instruction Address Break

• Data Bus break

• Processor Bus Break

• Reset, NMI, Interrupt Mask

5. Instructions for Debug

• SDBBP, DERET, CTC0, CFC0

6. CP0 Registers for Debug

• Debug, DEPC, DESAVE

9.2

EJTAG interface

This interface consists of two modes of operation a Run Time Mode and Real Time Mode. The

Run Time Mode provides functions such as processor Run, STOP, Single Step, and access to

internal registers and system memory. The Real Time mode provides additional status pins

used in conjunction with JTAG pins for Real Time Trace information.

Table 9.2.1 JTAG Interface

PIN NAME

I / O

FUNCTION

JTDI

JTAG data input / Debug interrupt input

Run-time mode: Input serial data to JTAG data/instruction registers.

Real-time mode: Interrupt input to change the debug unit state from real-time mode to run-time mode.

JTCK

JTAG clock input

Clock input for JTAG. The JTDI and JTMS data are latched on rising edges of this clock.

JTDO/TPC(0)

JTAG data output / Trace PC output

Data is serially shifted out from this pin. / Outputs a non-sequential program counter value

synchronously with DCLK.

JTMS

JTAG command

Controls mainly the status transition of the TAP controller state machine.

When the serial input data is a JTAG command, apply a high signal (= 1) to this pin.

DCLK

Debug clock (1/3 CPU clock)

Clock output for a real-time debug system. Timings of the serial monitor bus and PC trace interface

signals all are defined by this debug clock DCLK.

This Debug clock frequency is 1/3 that of Pclock.

PCST(8:0)

PC trace status

Outputs PC trace status information and serial monitor bus mode.

TPC(3:1) Note 1

Trace PC output

Outputs a non-sequential program counter value synchronously with DCLK.

TRST*

Test reset input

Reset input for a real-time debug system. When TRST* is asserted (= 0), the debug support unit (DSU)

is initialized.

Note1: Leave TPC (3-1) pins open when not using them as PC trace outputs for debugging.

TMPR4955AF Datasheet(PDF) 153 Page - Toshiba Semiconductor

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