PIC18F6310ESLASHPTSQTP datasheet(49/404 Pages) MICROCHIP

49 / 404 page

 2004 Microchip Technology Inc.

Preliminary

DS39635A-page 47

PIC18F6310/6410/8310/8410

TABLE 3-2:

EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE

(BY CLOCK SOURCES)

Clock Source

before Wake-up

Clock Source

after Wake-up

Exit Delay

Clock Ready Status

bit (OSCCON)

Primary Device Clock

(PRI_IDLE mode)

LP, XT, HS

TCSD(2)

OSTS

HSPLL

EC, RC, INTRC(1)

—

INTOSC(3)

IOFS

T1OSC or INTRC(1)

LP, XT, HS

TOST(4)

OSTS

HSPLL

TOST + trc

(4)

EC, RC, INTRC(1)

TCSD(2)

—

INTOSC(2)

TIOBST(5)

IOFS

INTOSC(3)

LP, XT, HS

TOST(5)

OSTS

HSPLL

TOST + trc

(4)

EC, RC, INTRC(1)

TCSD(2)

—

INTOSC(2)

None

IOFS

None

(Sleep mode)

LP, XT, HS

TOST(4)

OSTS

HSPLL

TOST + trc

(4)

EC, RC, INTRC(1)

TCSD(2)

—

INTOSC(2)

TIOBST(5)

IOFS

Note 1:

In this instance, refers specifically to the 31 kHz INTRC clock source.

TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently

with any other required delays (see Section 3.4 “Idle Modes”).

Includes both the INTOSC 8 MHz source and postscaler derived frequencies.

TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is

also designated as TPLL.

Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.

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