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ADV7393EBZ Datasheet(PDF) 29 Page - Analog Devices

Part # ADV7393EBZ
Description  Low Power, Chip Scale 10-Bit SD/HD Video Encoder
PDF  96 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV7393EBZ Datasheet(HTML) 29 Page - Analog Devices

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ADV7390/ADV7391/ADV7392/ADV7393
Rev. 0 | Page 29 of 96
Table 17. Register 0x31 to Register 0x33
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0
Pixel data valid off
0x00
ED/HD Pixel Data Valid.
1
Pixel data valid on
0
4×
HD Oversample Rate Select.
1
2×
0
HD test pattern off
ED/HD Test Pattern Enable.
1
HD test pattern on
0
Hatch
ED/HD Test Pattern Hatch/Field.
1
Field/frame
0
Disabled
ED/HD Vertical Blanking Interval (VBI)
Open.
1
Enabled
0
0
Disabled
0
1
−11 IRE
1
0
−6 IRE
ED/HD Undershoot Limiter.
1
1
−1.5 IRE
0
Disabled
0x31
ED/HD Mode
Register 2
ED/HD Sharpness Filter.
1
Enabled
0
0
0
0 clock cycles
0x00
0
0
1
1 clock cycle
0
1
0
2 clock cycles
0
1
1
3 clock cycles
ED/HD Y Delay with Respect to Falling
Edge of HSYNC.
1
0
0
4 clock cycles
0
0
0
0 clock cycles
0
0
1
1 clock cycle
0
1
0
2 clock cycles
0
1
1
3 clock cycles
ED/HD Color Delay with Respect to
Falling Edge of HSYNC.
1
0
0
4 clock cycles
0
Disabled
ED/HD CGMS Enable.
1
Enabled
0
Disabled
0x32
ED/HD Mode
Register 3
ED/HD CGMS CRC Enable.
1
Enabled
0
Cb after falling edge of HSYNC
0x68
ED/HD Cr/Cb Sequence.
1
Cr after falling edge of HSYNC
Reserved.
0
0 must be written to this bit
0
8-bit input
ED/HD Input Format.
1
10-bit input1
0
Disabled
Sinc Compensation Filter on DAC 1,
DAC 2, DAC 3.
1
Enabled
Reserved.
0
0 must be written to this bit
0
Disabled
ED/HD Chroma SSAF Filter.
1
Enabled
Reserved.
1
1 must be written to this bit
0
Disable
0x33
ED/HD Mode
Register 4
ED/HD Double Buffering.
1
Enabled
1 Available on the ADV7392/ADV7393 (40-pin devices) only.



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