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ICS951702 Datasheet(PDF) 4 Page - Renesas Technology Corp

Part # ICS951702
Description  PIII™ System Clock Chip for DDR SDRAM
PDF  13 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS951702 Datasheet(HTML) 4 Page - Renesas Technology Corp

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Serial Configuration Command Bitmap
ByteO: Functionality and Frequency Select Register (default = 0)
Bit
Description
FS3 FS2 FS1 FS0 CPUCLK SDRAM PCICLK
Bit2 Bit? Bit6 Bit5 Bit4
(MHz)
(MHz)
(MHz)
0
0
0
0
0
66.66
66.66
33.33
0
0
0
0
1
66.66
100.00
33.33
0
0
0
1
0
100.00
66.66
33.33
0
0
0
1
1
100.00
100.00
33.33
0
0
1
0
0
100.00
133.33
33.33
0
0
1
0
1
133.33
66.66
33.33
0
0
1
1
0
133.33
100.00
33.33
0
0
1
1
1
133.33
133.33
33.33
0
1
0
0
0
66.66
66.66
33.33
0
1
0
0
1
66.66
100.00
33.33
0
1
0
1
0
100.00
66.66
33.33
0
1
0
1
1
100.00
100.00
33.33
0
1
1
0
0
100.00
133.33
33.33
0
1
1
0
1
133.33
66.66
33.33
Bit 2,
0
1
1
1
0
133.33
100.00
33.33
Bit 7:4
0
1
1
1
1
133.33
133.33
33.33
1
0
0
0
0
69.99
69.99
35.00
1
0
0
0
1
69.99
105.00
35.00
1
0
0
1
0
105.00
69.99
35.00
1
0
0
1
1
105.00
105.00
35.00
1
0
1
0
0
105.00
140.00
35.00
1
0
1
0
1
140.00
69.99
35.00
1
0
1
1
0
140.00
105.00
35.00
1
0
1
1
1
140.00
140.00
35.00
1
1
0
0
0
73.33
73.33
36.66
1
1
0
0
1
73.33
110.00
36.66
1
1
0
1
0
110.00
73.33
36.66
1
1
0
1
1
110.00
110.00
36.66
1
1
1
0
0
110.00
146.66
36.66
1
1
1
0
1
146.66
73.33
36.66
1
1
1
1
0
146.66
110.00
36.66
1
1
1
1
1
146.66
146.66
36.66
Bit 3
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 1
0- Normal
1 - Spread Spectrum Enabled
Bit 0
0 - Running
1- Tristate all outputs
AGP
(MHz)
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
73.33
73.33
73.33
73.33
ICS951702
Advance Information
PWD
Spread Precentage
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
00000
0 to -0.5% Down Spread
Note1
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0
0
0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The 12C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
0664---07/29/02
4



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