12

Integrated

Circuit

Systems, Inc.

ICS954321

1078B—09/20/05

OE#

SRCCLK

Figure 2. OE# Control Tim ing

Power Stable to Device

TSRCSTBL

TPVCRL

VPCIEXDEV

SRCCLK

OE#

Figure 1. Power-Up OE# Tim ing

Symbol

Parameter

Min

Max

Units

TPVCRL

Power Valid to OE# Output Active (Fig. 1)

100

µs

TSRCSTBL

SRC Clock Stablilzation Time from assertion of OE#

(Fig. 1)

800

µs

1This timing is valid only after system clocks are stable.

Symbol

Parameter

Min

Max

Units

TCRHoff

OE# De-asserted High to SRCCLK Parked (Fig. 2)

0

µs

TCRHon

OE# Asserted LOW to SRCCLK Active (Fig. 2)

0.4

µs

Table 1. Power-Up OE# Timing1

Table 2. OE# Control Timing

OE# - Assertion (transition from logic "1" to logic "0")

The impact of asserting the OE# pin is that the SRCCLK output will become active per the timing found in the OE#

Control Timing Table. The clock will become active in a glitch free manner, providing a full cycle at the time it

becomes active.

OE# - De-Assertion (transition from logic "0" to logic "1")

The impact of asserting the OE# pin is that the SRCCLK output will become inactive setliing in the Tristate condition

per the timing found the OE# Control Timing Table. The clock will become inactive in a glitch free manner.