October 6, 2005 S75WS-N_02_A2

S75WS-N Based MCPs

5

Pr el im i n a r y

3

Input/Output Descriptions

Table 3.1 identifies the input and output package connections provided on the device.

Table 3.2 identifies the ORNAND input and output connections provided on the device.

Table 3.1 NOR Flash and RAM Input/Output Descriptions

Symbol

Description

Address Inputs

(Common)

DQ15 - DQ0

Data Inputs/Outputs

OE#

Output Enable input

WE#

Write Enable input

Ground

NC

No Connect; not connected internally.

RDY

Ready output. Indicates the status of the Burst read.

(Flash)

CLK

Clock input. In burst mode, after the initial word is output, subsequent

active edges of CLK increment the internal address counter. Should be at

(Common)

AVD#

Address Valid input.

Indicates to device that the valid address is present on the address inputs.

(Flash)

F-RST#

Hardware reset input.

F-WP#

Hardware write protect input.

F-ACC

Accelerated input.

R-CE#

Chip-enable input for pSRAM

F1-CE#

Chip-enable input for Code Flash.

Asynchronous relative to

CLK for Burst Mode.

F2-CE#

Chip-enable input for Data Flash 1.

F2-CE#

Chip-enable input for Data Flash 2.

R-MRS#

Control Register Enable.

(pSRAM – RAM Type 4 only)

Flash 1.8 Volt-only single power supply.

pSRAM Power Supply.

R-UB#

Upper Byte Control.

(pSRAM)

R-LB#

Lower Byte Control .

Table 3.2 ORNAND Flash Input/Output Descriptions

Symbol

Description

N-PRE

N-ALE

ORNAND Address Latch Enable

N-CLE

ORNAND Command Latch Enable

N-CE#

ORNAND Chip-enable

N-WP#

ORNAND Write-protect

N-WE#

ORNAND Write-enable

N-RE#

ORNAND Read-enable

N-RY/BY#

ORNAND Ready-Busy—this is shared with NOR RDY

N-I/O0-N-I/O15

ORNAND I/O signals (I/O0-I/O7 for x8 bus width)

ORNAND Power supply