DSPIC30F datasheet(27/220 Pages) MICROCHIP

27 / 220 page

 2004 Microchip Technology Inc.

Preliminary

DS70116C-page 25

dsPIC30F5011/5013

FIGURE 3-5:

DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

3.2

Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP instruc-

tions), or as one unified linear address range (for MCU

instructions). The data spaces are accessed using two

Address Generation Units (AGUs) and separate data

paths.

3.2.1

DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key element of this architecture is that

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent linear

addressing space, X and Y spaces have contiguous

addresses.

PSVPAG(1)

EA<15> = 0

EA<15> = 1

Data

Space

Data Space

Program Space

0x0000

0x8000

0xFFFF

0x21

0x108000

0x10FFFF

Data Read

Upper Half of Data

Space is Mapped

into Program Space

0x108200

Address

Concatenation

BSET

CORCON,#2

; PSV bit set

MOV

#0x21, W0

; Set PSVPAG register

MOV

W0, PSVPAG

MOV

0x8200, W0

; Access program memory location

; using a data space access

Note:

PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines

the page in program space to which the upper half of data space is being mapped).

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