BT261 datasheet(39/56 Pages) ETC

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Brooktree®

L261_H

INTERNAL REGISTERS

HCOUNT Register

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

HCOUNT Register

This 12-bit register speciﬁes the maximum number of pixel clocks to generate per horizontal line. In phase-locked

applications, HCOUNT is the critical register that is resolution dependent. It should be programmed with the number

of pixels per line required, minus 1. The other timing-dependent registers, including noise gate, ZERO, CLAMP, and

HSYNC, will now all be programmed in terms of clock events, based upon the number of clocks per line deﬁned in

HCOUNT. For example, the HSYNC stop register is programmed to set output low at count zero, signifying the fall-

ing edge of HSYNC or the beginning of the line. The HSYNC start value is programmed to toggle high at 4.75

µs into

the horizontal line, signifying the beginning of the back porch, for RS170A. The HSYNC start value in terms of a

12.27 MHz clock (square pixels NTSC) would be 59 clocks, or ~4.7

µs (see Figure 8).

The HCOUNT low and high registers are cascaded to form a 12-bit HCOUNT register. D4–D7 of HCOUNT high

are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 12-bit HCOUNT register

is not updated until the write cycle to the HCOUNT high register. Thus, the writing sequence should be [HCOUNT

low] [HCOUNT high]. Values from $0000 (1) to $0FFF (4096) may be speciﬁed. This register should be written ﬁrst

during initialization to minimize indeterminate output activity.

HCOUNT High

HCOUNT Low

Data Bit

Cascaded Value

H11

H19

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