VSC7121 datasheet(4/12 Pages) VITESSE

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC7121

Quad Port Bypass Circuit for 1.0625 Gbit/sec

Fibre Channel Arbitrated Loop Disk Arrays

Page 4

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

8/31/98

G52110-0, Rev. 4.1

Table 2: AC Characteristics (Over recommended operating conditions).

Table 3: DC Characteristics (Over recommended operating conditions).

Parameters

Description

Min.

Max.

Units

Conditions

Flow-Through Propagation Delay

Rising Edge to Rising Edge

7.0

Delay with all circuits bypassed. 75

Ohm Load

Flow through Propagation Delay

Falling Edge to Falling Edge

7.0

Delay with all circuits bypassed. 75

Ohm load.

TSDR, TSDF

Serial data rise and fall time

—

300

ps.

20% to 80%, tested on a sample basis

Parameters

Description

Min

Typ

Max

Units

Conditions

VIH(TTL)

Input HIGH voltage (SEL - TTL)

2.0

—

5.5

IIH < 6.6 mA @ VIH = 5.5 V

VIL(TTL)

Input LOW voltage (SEL - TTL)

—

0.8

—

IIH(TTL)

Input HIGH current (SEL- TTL)

—

500

µAV

IN = 2.4 V

IIL(TTL)

Input LOW current (SEL - TTL)

—

-500

µAV

IN = 0.5 V

VDD

Supply voltage

3.10

—

3.50

VDD = 3.30V + 5%

IDD

Supply current

—

170

Outputs open, VDD = VDD max

Power Dissipation

0.6

Outputs open, VDD = VDD max

∆V

IN(DF)

Receiver differential peak-to-peak

Input Sensitivity, IN+/- & L_SIn+/-

300

2600

mVp-p

AC Coupled.

Internally biased at VDD/2

∆V

OUT(L_SO)

L_SOn+/- output differential peak-

to-peak voltage swing

1000

—

2200

mVp-p

Ω to V

DD – 2.0 V

∆V

OUT(OUT)

OUT+/- output differential peak-to-

peak voltage swing

1200

2200

mVp-p

Ω to V

DD – 2.0 V

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