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MPC9817SD Datasheet(PDF) 5 Page - Renesas Technology Corp |
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MPC9817SD Datasheet(HTML) 5 Page - Renesas Technology Corp |
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5 / 8 page ![]() MPC9817 REVISION 3 AUGUST 16, 2012 5 ©2012 Integrated Device Technology, Inc. MPC9817 Data Sheet CLOCK GENERATOR FOR POWERQUICC AND POWERPC MICROPROCESSORS AND MICROCONTROLLERS Figure 3. MPC9817 AC Test Reference (LVCMOS Outputs) Table 7. AC Characteristics(1) (2) (VDD = 3.3 V ± 5%, TA = –40° to +85°C) 1. AC characteristics are design targets and pending characterization. 2. AC characteristics apply for parallel output termination of 50 to VTT. Symbol Characteristics Min Typ Max Unit Condition Input and Output Timing Specification fref Input Reference Frequency 25 MHz Input XTAL Input — 25 25 — MHz MHz — fVCO VCO Frequency Range — 400 — MHz — fMCX Output Frequency (QAx)FSEL0, FSEL1 = 00 FSEL0, FSEL1 = 01 FSEL0, FSEL1 = 10 FSEL0, FSEL1 = 11 Output Frequency (QREFx) — 25 33 50 66 25 — MHz MHz MHz MHz MHz PLL locked frefPW Reference Input Pulse Width 10 — — ns @ 25 MHz DC Output Duty Cycle 47.5 50 52.5 % — fout Output Frequency Accuracy Crystal(3) External Reference 3. Based upon recommended crystal specifications as outlined in MPC9817 Operation. — — 100 0 ppm ppm With recommended crystal see Table 3 PLL Specifications BW PLL Closed Loop Bandwidth(4) 4. –3 dB point of PLL transfer characteristics. — 500 — kHz — tLOCK Maximum PLL Lock Time — — 10 ms — Skew and Jitter Specifications tsk(O) Output-to-Output Skew (within a bank) — — 100 ps — tsk(O) Output-to-Output Skew (between bank A and bank Ref) — — 200 — FSEL0, FSEL1 = 00 tJIT(CC) Cycle-to-Cycle Jitter — — 150 ps @ 25 MHz Input Reference QA output tJIT(PER) Period Jitter — — 100 ps @ 25 MHz Input Reference QA output tr, tf Output Rise/Fall Time — — 1 ns 20% to 80% Z = 50 RT = 50 VTT Z = 50 VTT DUT MPC9817 Pulse Generator Z = 50 RT = 50 |
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