ADF4193BCPZ datasheet(21/28 Pages) AD

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ADF4193

Rev. B | Page 21 of 28

MUX REGISTER (R6)

DB15

M13

DB14

M12

DB13

M11

DB12

M10

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C3 (1)

DB1

C2 (1)

DB0

C1 (0)

RESERVED

MUXOUT

CONTROL

BITS

SIGMA-DELTA

AND

LOCK DETECT MODES

M10

M11

ALL OTHER STATES

M12

M13

INIT STATE, DITHER OFF,

3ns LOCK DETECT THRESHOLD

DITHER ON

10ns LOCK DETECT THRESHOLD

RESERVED

SIGMA-DELTA MODES

3-STATE

DIGITAL LOCK DETECT

N DIVIDER OUTPUT

LOGIC HIGH

R COUNTER

RESERVED

SERIAL DATA OUT

LOGIC LOW

R DIVIDER/2 OUTPUT

N DIVIDER/2 OUTPUT

RESERVED

ICP TIMEOUT SIGNAL

SW1/2 TIMEOUT SIGNAL

SW3 TIMEOUT SIGNAL

RESERVED

MUXOUT

Figure 35. MUX Register (R6)

With C3, C2, and C1 set to 1, 1, 0, respectively, the MUX

Σ-Δ and Lock Detect Modes

Bit DB15 to Bit DB12 are used to reconfigure certain PLL

operating modes. In the initialization sequence after power is

applied to the chip, the four bits must first be programmed to

all zeros. This initializes the PLL to a known state with dither

off in the Σ-Δ modulator and a 3 ns PFD error threshold in the

lock detect circuit.

To turn on dither in the Σ-Δ modulator, an additional write

should be made to Register R6 to program bits [DB15:DB12] =

[0011]. However, for lowest noise operation, it is best to leave

dither off.

To change the lock detect threshold from 3 ns to 10 ns, a

separate write to R6 should be performed to program bits

[DB15:DB12] = [1001]. This should be done for reliable lock

detect operation when the RF frequency is <2 GHz.

A write to R6 that programs bits [DB15:DB12] = [0000] returns

operation to the default state with both dither off and a 3 ns

lock detect threshold.

Reserved Bits

The reserved bits must all be set to 0 for normal operation.

MUXOUT Modes

These bits control the on-chip multiplexer. See Figure 35 for the

truth table. This pin is useful for diagnosis because it allows the

user to look at various internal points of the chip, such as the

R divider and INT divider outputs.

In addition, it is possible to monitor the programmed timeout

counter intervals on MUXOUT. For example, if the ICP timeout

counter was programmed to 65 (with a 26 MHz PFD), then

following the next write to R0, a pulse width of 10 μs would be

observed on the MUXOUT pin.

Digital lock detect is available via the MUXOUT pin.

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