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AD5384BBC-5 Datasheet(PDF) 30 Page - Analog Devices |
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AD5384BBC-5 Datasheet(HTML) 30 Page - Analog Devices |
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30 / 36 page  AD5384 Rev. A | Page 30 of 36 2-Byte Mode Following initialization of 2-byte mode, the user can update channels sequentially. The device address byte is required only once, and the pointer address pointer is configured for auto- increment or burst mode. The user must begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF) that initiates the burst mode of operation. The address pointer initializes to Channel 0,and, upon receiving the two data bytes for the present address, automatically increments to the next address. The REG0 and REG1 bits in the data byte determine which register is updated. In this mode, following the initialization, only the two data bytes are required to update a channel. The channel address automatically increments from Address 0. This mode allows transmission of data to all channels in one block and reduces the software overhead in configuring all channels. A stop condition at any time exits this mode. Toggle mode is not supported in 2-byte mode. Figure 31 shows a typical configuration. 1 0 1 0 1 AD1 AD0 R/W 0 0 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1 START COND BY MASTER ADDRESS BYTE POINTER BYTE MOST SIGNIFICANT DATA BYTE CHANNEL 0 DATA LEAST SIGNIFICANT DATA BYTE ACK BY AD538x MSB ACK BY AD538x ACK BY AD538x ACK BY AD538x MOST SIGNIFICANT DATA BYTE CHANNEL 1 DATA LEAST SIGNIFICANT DATA BYTE ACK BY AD538x ACK BY CONVERTER MOST SIGNIFICANT DATA BYTE CHANNEL N DATA FOLLOWED BY STOP LEAST SIGNIFICANT DATA BYTE ACK BY AD538x ACK BY CONVERTER STOP COND BY MASTER REG1 REG0 MSB LSB MSB LSB REG1 REG0 MSB LSB MSB LSB REG1 REG0 MSB LSB MSB LSB SCL SDA SCL SDA SCL SDA SCL SDA Figure 31. 2-Byte, 12C Write Operation |
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