AD5384BBC-5 datasheet(26/36 Pages) AD

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AD5384

Rev. A | Page 26 of 36

INTERFACES

The AD5384 contains a serial interface that can be

programmed either as DSP-, SPI-, MICROWIRE-, or I2C-

compatible. The SPI/I2C pin is used to select DSP, SPI,

MICROWIRE, or I2C interface mode. To minimize both the

power consumption of the device and the on-chip digital noise,

the active interface powers up fully only when the device is

being written to, i.e., on the falling edge of SYNC.

DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL

INTERFACES

The serial interface can be operated with a minimum of three

wires in standalone mode or five wires in daisy-chain mode.

Daisy chaining allows many devices to be cascaded together to

increase system channel count. The SPI/I2C (Ball B8) should be

tied high to enable the DSP-, SPI-, MICROWIRE-compatible

serial interface. The serial interface control pins are

SYNC, DIN, SCLK—Standard 3-Wire Interface Pins.

DCEN

—Selects Standalone Mode or Daisy-Chain Mode.

SDO

—Data Out Pin for Daisy-Chain Mode.

Figure 3 and Figure 5 show the timing diagrams for a serial

write to the AD5384 in standalone and in daisy-chain modes.

The 24-bit data-word format for the serial interface is shown in

Table 20.

A/B. When toggle mode is enabled, this selects whether the

data write is to the A or B register, with Toggle disabled this bit

should be set to zero to select the A data register.

R/W is the read or write control bit.

A5–A0

are used to address the input channels.

REG1

and REG0 select the register to which data is written, as

shown in Table 12.

DB13–DB0

contain the input data-word.

is a don’t care condition.

Standalone Mode

By connecting DCEN (daisy-chain enable) pin low, standalone

mode is enabled. The serial interface works with both a

continuous and a noncontinuous serial clock. The first falling

edge of SYNC starts the write cycle and resets a counter that

counts the number of serial clocks to ensure that the correct

number of bits are shifted into the serial shift register. Any

further edges on SYNC, except for a falling edge, are ignored

until 24 bits are clocked in. Once 24 bits are shifted in, the

SCLK is ignored. For another serial transfer to take place, the

counter must be reset by the falling edge of SYNC.

Table 20. 40-Channel, 14-Bit DAC Serial Input Register Configuration

MSB

LSB

A/B

R/W

REG1

REG0

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

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