Nexperia

74LVC1G58

Low-power configurable multiple function gate

7.1. Logic configurations

Table 5. Function selection table

Logic function

Figure

2-input NAND

see Fig. 5

2-input NAND with both inputs inverted

see Fig. 8

2-input AND with inverted input

see Fig. 6 and Fig. 7

2-input NOR with inverted input

see Fig. 6 and Fig. 7

2-input OR

see Fig. 8

2-input OR with both inputs inverted

see Fig. 5

2-input XOR

see Fig. 9

Buffer

see Fig. 10

Inverter

see Fig. 11

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B

B

6

Y

C

1

5

2

4

3

Y

Y

C

B

C

VCC

Fig. 5. 2-input NAND gate or

2-input OR with both inputs inverted

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B

B

6

Y

C

1

5

2

4

3

Y

Y

C

B

C

VCC

Fig. 6. 2-input AND gate with inverted B input or

2-input NOR gate with inverted C input

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A

A

6

Y

C

1

5

2

4

3

Y

Y

C

A

C

VCC

Fig. 7. 2-input AND gate with inverted C input or

2-input NOR gate with inverted A input

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A

6

C

1

5

2

4

3

Y

VCC

A

Y

C

Y

A

C

Fig. 8. 2-input OR gate or

2-input NAND gate with both inputs inverted

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B

6

C

1

5

2

4

3

Y

VCC

Y

B

C

Fig. 9. 2-input XOR gate

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A

A

6

Y

1

5

2

4

3

Y

VCC

Fig. 10. Buffer

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B

B

6

Y

1

5

2

4

3

Y

VCC

Fig. 11. Inverter

74LVC1G58

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Product data sheet

Rev. 11 — 1 February 2022

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