PCK9446_1

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 10 April 2006

3 of 17

Philips Semiconductors

PCK9446

2.5 V and 3.3 V LVCMOS clock fan-out buffer

5.

Pinning information

5.1 Pinning

5.2 Pin description

[1]

Fig 2.

Pin configuration for LQFP32

PCK9446BD

CLK_SEL

GND

QB0

CLK0

VCCB

CLK1

QB1

FSELA

GND

FSELB

QB2

FSELC

VCCB

GND

VCCC

002aaa706

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

Table 2.

Pin description

Symbol

Pin

I/O

Type

Description

CLK_SEL

1

I

clock input select

CLK0, CLK1

3, 4

I

LVCMOS

LVCMOS clock inputs

FSELA, FSELB,

FSELC

5, 6, 7

I

LVCMOS

output bank divide select input

MR/OE

32

I

LVCMOS

internal reset and output 3-State control

GND

8, 11, 15, 20,

24, 27, 31

supply

negative voltage supply output bank

(GND)

VCCA

25, 29

supply

positive voltage supply for output bank A

VCCB[1]

18, 22

supply

positive voltage supply for output bank B

VCCC

9, 13, 17

supply

positive voltage supply for output bank C

2

supply

QA[0:2]

30, 28, 26

O

LVCMOS

bank A outputs

QB[0:2]

23, 21, 19

O

LVCMOS

bank B outputs

QC[0:3]

10, 12, 14, 16

O

LVCMOS

bank C outputs